TRAVEO™ T2G

你好，在调试基于CYT2B7的产品板时，遇到一个很奇怪的现象，能帮忙分析下可能的原因吗？

PCB板上有多个电源轨， MCU和SPI slave设备分别是两个不同的电源轨供电，不同电源之间是供地的，且电压是一致的；

如果MCU电源断电，此时所有MCU管脚应该是低电平，由于SPI设备并未断电，所以SPI slave设备的1脚CS信号由于存在上拉，所以期望是高电平，保证SPI设备不被选中；

但实测发现，MCU断电后，即使SPI设备正常供电，片选信号CS(MCU1_SCS0_SPI2)被拉低了;

如果此时把与MCU串接的电阻(R1)断开，则片选信号CS恢复高电平；

针对不同MCU引脚飞线都做了上述测试，结果一致；

我们怀疑MCU断电后，通过MCU管脚的体二极管向MCU内部灌入电流，导致外部设备上拉无效；

这种情况可能吗？如果不存在此种情况，那是什么原因导致MCU断电后，外部上拉无效呢？

期待你的回复，谢谢~~

hello, 

I am trying to  generate hex and elf file with cmakelists for blink led project.

I am also using IAR files from the traveo SDL folder tviibe1m.

Unfortunately, I am not able to create the hex and elf even the compilation is without errors.

Would appreciate if you can review my project.

thanks,

Hi, 

Going thoroughly through CYT4BF datasheets and TRM, I see that the MCU has 2 M_TTCAN controller with 5 channels each. What are the limitations of such an arrangement? Typically, MCUs use a 1:1 mapping controller to channel. 

Basically I'm looking to answer these questions:

1. Does this arrangement have any hidden limitations that are not clear?

2. Can all channels operate independently at a different bit rate at full CAN-FD capacity of 5Mbps at the same time (that is - all 5 channels connected to active peripherals operating full speed of 5Mbps at the same time)?

3. If there are shared functions that cause performance impacts, what are they?

Thank you for your support!

Vai

参考SDL7.3 :T2G_Sample_Driver_Library_7.3.0\tviibe1m\src\examples\flash\code\cm0_cm4_non_blocking 文件夹下示例验证non-blocking 操作flash；

有如下疑问，请帮忙解答：

在调用Cy_FlashInit时，虽然是初始化non-blocking模式，

但在后续Cy_FlashWriteCode()函数里，在调用Cy_Flash_ProgramRow之前初始化参数时，

programRowConfig.blocking仍是按blocking模式进行设置，那最终program还是blocking啊

这个地方为什么要做这样的配置呢？

另：TraveoII中Flash Macro的数量有多少呢？TRM手册或代码中都没有体现？

Hi ,

Is it possible to create a single hex file from two different srec files  that can be used to to flash the Bank A and Bank B  in a single command using miniprog ? 

Regards

Gokul