TRAVEO™ T2G Forum Discussions

Hello,

I would to ask what will be netto weight per unit :

CYT2BL8CAAQ0AZEGS in LQFP assembly ?

Part is from : 

32-bit Arm® Cortex®-M4F microcontroller
TRAVEO™ T2G family

I must know netto weigh per unit for custom service.

ご担当者様

TRAVEOⅡのSCB(UART)でSmartCard (ISO7816)に対応していることを確認いたしました。

SmartCard (ISO7816)のサンプル・プログラム(あるいはドライバ)は提供可能でしょうか。

ご確認のほどよろしくお願いいたします。

Dears,

While doing OpenOCD based Auto Flash Util 1.2 programming through Miniprog4, "KitProg3: Pipelined transfers disabled, please update the firmware" message appears. In this case, KitProg3: FW version is  1.1.158. Meanwhile after updating Auto Flash Util 1.3 and KitProg3: FW version: 2.21.1005, "KitProg3: Pipelined transfers enabled" appears. What I want to know is what the difference between "enabled" and "disabled" in terms of functionality as well as is it related to programming pass/fail?

Thanks,

Jin

Hello,

I'm asking support for the ECC Error Injection into SRAM, in order to implement a RAM test for a safety function. The chapter 10.3.3 of Technical Reference Manual report the following instruction, to generate a fault:

The fault reporting structure for ECC faults can be debugged through an SRAM controller ECC parity injection mechanism.
This mechanism functions as follows:
■ ECC injection is enabled through CPUSS_RAMx_CTL0.ECC_INJ_EN (for SRAM controller x).
■ A word address is specified by CPUSS_ECC_CTL.WORD_ADDR[23:0]
(CPUSS_ECC_CTL.WORD_ADDR = (0x00FFFFFF & (RAM_TEST_ADDRESS>>2))).
■ A 8-bit parity is specified by CPUSS_ECC_CTL.PARITY[7:0].
When a write transfer to the specified word address is performed, the ECC parity generation uses the specified 8-bit parity,
rather than the calculated parity. The data still originates from the bus transfer. Any access size can be used to inject parity.

So, based on these indications, i define a RamTest variable, and write its address on CPUSS_ECC_CTL.WORD_ADDR (where to inject the error):

CYREG_CPUSS_ECC_CTL->stcField.u24WORD_ADDR = (0x01FFFFFF & ((uint32_t)&u64_VfSelfTest_RAMTest>>2));

write a parity to inject as an error:

CYREG_CPUSS_ECC_CTL->stcField.u8PARITY = 0x5A;

enable the injection:

CYREG_CPUSS_RAM0_CTL0->stcField.u1ECC_INJ_EN = 1u;

and at least write and read the variables, to generate error, wich should be reported by fault reporting structure (FAULT_STRUCT_STATUS, Description: Fault status, Address: 0x4021000C). But at the moment the FAULT_STRUCTx_STATUS.VALID still remains set to ‘0’ (no fault) and no fault interrput is generate.

What is wrong?

Thanks for the support

Dear Sirs:

      Do you know which type of  CYT4BF's Flexray Communication controller belongs to? Thanks.

Hello,

I'm asking support for the configuration shown on Lauterbach debugger for MPU. 

On  Region 3 address 0x28018000 I allocate a variable in RAM as shown on watch window called:  “VF_Safe_u8DebugCnt”.

Region 3 overlaps Region 0 considered as background but I'm using logic of priority based on Region ID higher wins  so I expect that Region 3 setting are the actual applied for this section where my variable is.

Region 3 for the instant I set the breakpoint is Disabled but it is still visible and modifiable by an increment operation done by my task.

I expected on exception or at least the impossibility to modify it.

As suggested on other forum, Region 3 has no cache.

Hi ;

TraveoII基于IAR编译环境，可以通过Option->output converter来把输出hex文件转换为BIN格式，但是此处生成的BIN是全部Flash区域的数据，存在很多填充的全0数据；

如果只需要把某一段有效区域的hex转换为BIN，需要通过Post-build command调用 ielftool 工具来转换，

但是参考 IAR 提供的示例：IELFTOOL Checksum - When using NXP LPC devices | IAR Systems；

在Post-build command执行响应的批处理指令时，编译后提示fatal error (批处理指令错误)；

请问有验证通过的Post-build command脚本文件，转换指定区域的hex格式为BIN吗？

Hi

What is the MPU_PASR[18] bit in the ARM®v7-M Architecture Reference Manual used to set in Traveo2?

https://developer.arm.com/documentation/ddi0403/latest

Checking B3-641 in the same document and other companies' documents, it seems to be a bit that sets whether or not it can be shared when multicore is used.

●If this idea is correct, is this bit irrelevant except when using multi-cores?

●Also, is there any documentation on MPU_PASR[18] (Sbit) in Traveo2?
(I would like documentation with explanations and usage examples)

Best Regards

Haya