TRAVEO™ T2G Forum Discussions

I am currently working PWM module in CYT4BF8CDS Microcontroller.

 Pwm_Init() API in having clock parameter its having default clock source. If change the Clock in that API doesn't take the clock.

I couldn't able to find where it is the issue on that.

Is there any possible to change the clock source in PWM ?

If possible Could you please do the Needful.

Hello: Recently, during motor development, I used SPI to control the MOS driver and turn the motor on and off. The following problems occur when sending data via SPI in PWM interrupt. 1. Using Cy_SCB_SPI_Transfer function to send, query the send status, the bit is always in the state of sending, resulting in the program has been stopped here, not in the interrupt to send can be sent to complete.2. Using Cy_SCB_SPI_WriteArray function can finish sending in PWM interrupt, but can't read the data received by SPI synchronously.Thanks. 2923328@qq.com Mr Wild 24.04.03

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/TRAVEO-T2G/%E5%9C%A8PWM%E4%B8%AD%E6%96%AD%E4%B8%AD%E9%80%9A%E8%BF%87SPI%E5%8F%91%E9%80%81%E6%95%B0%E6%8D%AE%E5%A4%B1%E8%B4%A5/td-p/727702

How to configure 2 pll phase-locked loops as cpu's clock in cyt4bb7, exactly how to configure pll to CLK_HF1 to be used as cpu's clock source, is there any detailed reference routines, and clock tree structure diagram of cyt4bb7.

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/TRAVEO-T2G/%E5%85%B3%E4%BA%8Ecyt4bb7%E5%A6%82%E4%BD%95%E5%B0%86pll%E9%94%81%E7%9B%B8%E7%8E%AF%E9%85%8D%E7%BD%AE%E4%B8%BAcpu%E6%97%B6%E9%92%9F/td-p/727830

Hello: Recently, during motor development, I used SPI to control a MOS driver to turn on and off the motor.

The following problem occurs when sending data via SPI in PWM interrupt.

1. Use Cy_SCB_SPI_Transfer function to send, query the sending status, the bit is always in the state of sending, resulting in the program has been stopped here, not in the interrupt send to send can be sent to complete.

2. Using Cy_SCB_SPI_WriteArray function can finish sending in PWM interrupt, but can't read the data received by SPI synchronously.

Thanks. 2923328@qq.com

Mr Wild 24.04.03

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MPN: CYT2B75BADQ0AZEGST The datasheet has labeled the ESD immunity of this material, and the HBM and CDM models are only the minimum, does it mean that there is no upper limit to the V-esd withstood? There is no technical documents as a support. In addition, CDM1 inside the corner pin refers to those PIN?

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/TRAVEO-T2G/CYT2B75BADQ0AZEGST-ESD%E6%8A%97%E5%B9%B2%E6%89%B0%E8%83%BD%E5%8A%9B%E9%97%AE%E9%A2%98/td-p/726716