TRAVEO™ T2G Forum Discussions

I am trying to drive a motor with PWM using TRAVEO T2G CYT2B7's MCU, but I have a question.

1. What is the difference between TCPWM for motor control and general TCPWM?

2. I want to use Full Bridge (H-Bridge) to control motors (forward, reverse, speed control, etc.).   Should I use a dedicated TCPWM for motor control or can I use a general TCPWM?

3. Or is it possible to use two (High Side) motor control TCPWMs and two (Low Side) general TCPWMs?

4. Are there any precautions when controlling H-Bridge motors?

Controller fault subsystem issue

• Controller fault subsystem is always capturing below faults at bootup((as soon as startup code calls main function).
• fault index 0x3d is non-correctable ECC error and Data[0] is pointing to SRAM initialization address "08005800".

0x3d: RAMC1_NC_ECC: System SRAM 1 non-correctable ECC error. See RAMC0_C_ECC description.

0x1d: MS_PPU_1: Peripheral interconnect, master interface 1 PPU. See MS_PPU_0 description.

0x3c: RAMC1_C_ECC: System SRAM 1 correctable ECC error. See RAMC0_C_ECC description

How do i find root cause and fix this issue?

Thanks in advance 

Hello community, I'm using MiniProg 4 debugger to flash the program to the Cypress Traveo T2G MCU. 

I want to view the memory dump of running code, I want to know which tool I should use for this purpose and a guide on this would be helpful.

请教一下各位：

          我在做安全启动的过程中，配置完TOC2和public key这些内容之后，如何计算新的sflash的hash值遇到一些疑惑：

1、sflash计算hash的地址范围是整个sflah吗？

2、计算出来的新的secure_HASH如何写入到efuse中呢？

I found the input buffer enabled at unused GPIO pins on 2.1 of KBA232509 as below URL.
https://community.infineon.com/t5/Knowledge-Base-Articles/Traveo-II-Automotive-Body-Controller-FAQ-GPIO-KBA232509/ta-p/266733
Is this the GPIO state after reset?

I confirmed that the input buffer is disabled with the default register settings on TV2BE-4M register TRM as below.
GPIO_PRTx_CFG . IN_EN0[3:3]=0 ; input buffer disabled

Which one is correct at the GPIO status after reset?
Also, if the KBA is correct (input buffers are enabled), Which documentation can I confirm that it is correct?

thank you,

功能：CYT4BF8CED中用SWPF禁用M0核中一段地址，

如下代码所示

CY_SECTION(".cy_sflash_app_prot") __USED static const cy_stc_si_app_prot_t cy_si_appprot =
{
.objSize = OBJECT_SIZE, /* Application Protection Object Size (in bytes) */
.n_fwpu = N_FWPU, /* Number of FWPU Max 16 */

/* Add FWPU configuration here, if you need additional FWPU region */
.fwpu0_adr.addr30 = 0x10038000u>>2ul, /* Region address */
.fwpu0_size.region_size = 0x8000, /* in bytes (multiple of 4) */
.fwpu0_size.enable = APP_PROT_ENABLE, /* FWPU0 enable */
.fwpu0_sl_att.urw = APP_PROT_ALLOW, /* FWPU0 Slave Attribute */
.fwpu0_sl_att.prw = APP_PROT_ALLOW, /* FWPU0 Slave Attribute */
.fwpu0_sl_att.ns = APP_PROT_ALLOW, /* FWPU0 Slave Attribute */
.fwpu0_sl_att.pc_mask = 0x007F, /* FWPU0 Slave Attribute */

/* bit0: PC0 mask (0: Prohibit, 1: Allow) */
/* : */
/* bit7: PC7 mask */
/* bit[8:15]: 0 */
.fwpu0_ms_att.urw = APP_PROT_ALLOW, /* FWPU0 Master Attribute */
.fwpu0_ms_att.prw = APP_PROT_ALLOW, /* FWPU0 Master Attribute */
.fwpu0_ms_att.ns = APP_PROT_ALLOW, /* FWPU0 Master Attribute */
.fwpu0_ms_att.pc_mask = 0x007F, /* FWPU0 Master Attribute */
};

然后在main函数中对0x10038000地址进行flash擦写操作，但成功了，为什么？看文档说PCMASK的8位是只对这段地址进行8等分，0x7F就是这段地址的第8份进行禁用访问设置，但是我把地址改为0x1003F000时也能进行擦写。这段区域所有地方都能进行访问。

但是经过我无数次的尝试，发现一个现象，当PC_MASK改为0x0004时就能禁用访问，且是这个段区域所有地方都能被禁用，（ps:0x0004这里指第3位为1，就能复现这个效果，0xF7也行）不知道为什么，是我什么配置错了吗？

然后我看论坛上的一个github代码，都会在main函数用下面这两个接口，参数我是如下配置的

Cy_Prot_ConfigBusMaster(CPUSS_MS_ID_CM0, true, true, (PC_MASK_OF_PC7));
Cy_Prot_SetActivePC(CPUSS_MS_ID_CM0, (PC_MASK_OF_PC7)); 

然后利用READSWPU和WRITE SWPU两个接口，如下

apiArg.r.opCode = 0x2C; /* ReadSWPU */
apiArg.r.puType = 0; /* Flash Write */
apiArg.r.puId = 0; /* for sector 128 is included in index 0 */
apiArg.r.dataAddr = (uint32_t)&apiData; /* SRAM_DATA_ADDRESS */
apiResult = Cy_Srom_CallApi((un_srom_api_args_t *)&apiArg, &apiResp);

if ((apiResult == CY_SROM_DR_SUCCEEDED) &&
((apiResp.resp[0] & API_RESULT_MASK) == API_RESULT_SUCCESS))
{
apiArg.w.opCode = 0x2D; /* WriteSWPU */
apiArg.w.control = 0; /* Update SWPU */
apiArg.w.puType = 0; /* Flash Write */
apiArg.w.puId = 0; /* for sector 128 is included in index 0 */
apiArg.w.dataAddr = (uint32_t)&apiData;
apiData.slAtt.pcMask = 0x007F;
apiResult = Cy_Srom_CallApi((un_srom_api_args_t *)&apiArg, &apiResp);

if ((apiResult == CY_SROM_DR_SUCCEEDED) &&
((apiResp.resp[0] & API_RESULT_MASK) == API_RESULT_SUCCESS))
{
    ret = true;
}
else
{
    ret = false;
}
}
else
{
    ret = false;
}

发现现象和之前的一样，上述代码均在M0+核中实现，

望解答！

Hi Infineon,

目前使用CYT2B73BADQ0AZSGS进行项目开发的时候遇到在IAR里已经download成功，复位或者重新上电后无法保持下载的程序；测试条件和料号如下：

1、TRACE Code ：CYT2B73BADQ0AZSGS，这是一颗单核M4 的MCU；如下图片；

2、IAR开发版本和最小系统原理图

3、CYT2B73BADQ0AZSGS  Debug正常 ，复位或者重新上电后MCU没有任何反应

4、如果是单核的M4 MCU，发现一个现象，M0+也可以DEGUG，但是无法执行单步调试，一直在0xffff fffe地址中循环，相关配置和执行步骤如下图：（如果是单核，M0应该不能Debug才对阿）

5、请教一下关于Cy_SysEnableApplCore(CY_CORTEX_M4_APPL_ADDR)函数，参数CY_CORTEX_M4_APPL_ADDR的地址是多少阿？

6、上传的Code,工程打开路径，如下图：

以上问题请帮忙分析一下，谢谢！

Hi

I am using CYT4BF and checking ITCM and DTCM.

You can see CM7 ITCM/DTCM, CM7_0 ITCM/DTCM, and CM7_1 ITCM/DTCM through the address map in the CYT4BF datasheet.

Looking at the CPU Subsystem, each core is marked as having an ITCM/DTCM memory area.

These areas seem to be CM7_0 ITCM/DTCM and CM7_1 ITCM/DTCM, but the CM7 ITCM/DTCM area is not visible.

Q1 : What is the CM7 ITCM/DTCM area? Where can I find out?

Q2 : What is the difference between CM7 ITCM/DTCM, CM7_0 ITCM/DTCM and CM7_1 ITCM/DTCM?

Thank you.

MSV