TRAVEO™ T2G Forum Discussions

To write data to flash on Traveo 2 processors, a sector erase must be performed first, but when performing a sector erase, a 32-bit address is cleared. Even if I wanted to print an 8-bit value, I would waste the life of the 32-bit address. For this reason, I want to use Flash EEPROM emulation. Is there a source file for this?

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I found that in the CYT 4B CM0 core, the timer interrupt cannot be used to CPUIntIdx0_IRQn to the CPUIntIdx2_IRQn, otherwise the interrupt cannot be entered, please why

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i want to configure CANFD for 8MBPS baudrate could u please helpme out how to configure ? i have configured for 2mbps it was working fine.but not able to configure for 8mbps there is a sync issue between canoe and controller i am getting Canfd Tx error. is there any data sheet for canfd baudrate calculator. please support. and also we are using TJA1463A transciver it will support upto 8mpbs baudrate. and the clock frequency is 80mhz Show Less

Hello Infineon Team, I have read the below mentioned article and planning to use this design. In my project the port is having only 2 supported smart IO's pins (Example: P13.0 & P13.1) P13.1 is already used for some purpose and P13.0 alone can be feed it as input (I.e in this filter design). But in this design seems to be 3 port pins is required (Ex. P13.0, P13.1, P13.2). Could please suggest an idea that and it can be used as one port pin alone to get an exact this filter output?? https://community.infineon.com/t5/Knowledge-Base-Articles/Digital-Glitch-Filter-with-configurable-Filtering-length-using-Smart-IO-in/ta-p/446251 Show Less

Good day together,

I´m new with Traveo.

My scenario:

1) CM7_0 core started by CM_0+ core (working)

2) CM7_0 core to start CM7_1 (working)

3) CM7_0 core to stop CM7_1: here I need first to put CM7_1 to Sleep. Question: as far as I understood (acc. infineon example code) one way is to use IPC.

Is there any other alternative and more direct way to let a core send another core to sleep mode?

I´d like to avoid to use IPC infrastructure.

For example with Tricore one core can "easily" stop another core by directly manipulating the CSFR register of the core to be stopped.

Thanks in advance for any input.

Ivan

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When I was developing bootloader, the client needed to keep the erasure and writing of flash in the MCU safely. It was necessary to separate the erasure and writing operations of flash to make flash driver. Each upgrade sends the flash driver through the host computer to the mCU to run in ROm. Now the problem is how to make flash driver?

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