My task ist to send a big block of data via UART.
Therefore I try to setup 2D DMA to feed the UART Tx FIFO.
I can trigger the DMA transfers by SW but I get no trigger by the UART FIFO threshold.
I read a lot of documentation, the example code and did some experiments - but without success.
I am not sure about:
- is there example code for my use case?
- is the trigger output of the SCB level or edge type?
- what type of trigger is needed by DMA
- setting for DMA / WAIT_FOR_DEACT
My setup:
Traveo II tviibe2m
UART SCB7
DMA DW1 / Ch 22
Trigger TRIG_IN_1TO1_8_SCB_TX_TO_PDMA17
DMA config
static cy_stc_pdma_descr_config_t stcDmaDescrConfig = {
/* DESCR_CTL WAIT_FOR_DEACT */ .deact = CY_PDMA_WAIT_FOR_REACT, /* Wait for trigger de-activation -> This is probably wrong. */
/* DESCR_CTL INTR_TYPE */ .intrType = CY_PDMA_INTR_DESCR_CMPLT, // CY_PDMA_INTR_X_LOOP_CMPLT,
/* DESCR_CTL TR_OUT_TYPE */ .trigoutType = CY_PDMA_INTR_X_LOOP_CMPLT, // CY_PDMA_INTR_1ELEMENT_CMPLT, // CY_PDMA_TRIGOUT_DESCR_CMPLT, // das hat es leider noch nicht gebracht.
/* DESCR_CTL CH_DISABLE */ .chStateAtCmplt = CY_PDMA_CH_ENABLED,
/* DESCR_CTL TR_IN_TYPE */ .triginType = CY_PDMA_TRIGIN_XLOOP,
/* DESCR_CTL DATA_SIZE */ .dataSize = CY_PDMA_BYTE, // size of a single transfer
/* DESCR_CTL SRC_TRANSFER_SIZE */ .srcTxfrSize = CY_PDMA_TXFR_SIZE_DATA_SIZE, // CY_PDMA_TXFR_SIZE_DATA_SIZE as per data size register; CY_PDMA_TXFR_SIZE_WORD 32-Bit
/* DESCR_CTL DST_TRANSFER_SIZE */ .destTxfrSize = CY_PDMA_TXFR_SIZE_WORD, // CY_PDMA_TXFR_SIZE_DATA_SIZE as per data size register; CY_PDMA_TXFR_SIZE_WORD 32-Bit
/* DESCR_CTL DESCR_TYPE */ .descrType = CY_PDMA_2D_TRANSFER,
/* DESCR_SRC */ .srcAddr = NULL, // This will be filled by the config function with pointer from application.
/* DESCR_DST */ .destAddr = (uint32_t *)&CY_USB_SCB_TYPE->unTX_FIFO_WR.u32Register,
/* DESCR_X_CTL SRC_X_INCR */ .srcXincr = 1,
/* DESCR_X_CTL DST_X_INCR */ .destXincr = 0, // HW-FIFO of the SCB
/* DESCR_X_CTL X_COUNT */ .xCount = E_UART_TRANSFER_SIZE - 1, // 128 would assume that UART is idle on start of transmission. A trigger leads to xCount + 1 transfers. Limit is 255.
/* DESCR_Y_CTL SRC_Y_INCR */ .srcYincr = E_UART_TRANSFER_SIZE, // Amount transfered after one trigger
/* DESCR_Y_CTL DST_Y_INCR */ .destYincr = 0, // HW-FIFO of the SCB
/* DESCR_Y_CTL Y_COUNT */ .yCount = DW_2D_LOOP - 1, // 2D transfer: there will be yCount + 1 transfers of size xCount + 1
/* DESCR_NEXT_PTR */ .descrNext = &stcDescr
};
Trigger Channel
Cy_TrigMux_Connect1To1( (TRIG_IN_1TO1_8_SCB_TX_TO_PDMA17), // TRIG_IN_1TO1_8_SCB_TX_TO_PDMA17 = 0x0000180Eu, /* From scb[7].tr_tx_req to cpuss.dw1_tr_in[22] */
(TRIG_OUT_1TO1_8_SCB_TX_TO_PDMA17), // TRIG_OUT_1TO1_8_SCB_TX_TO_PDMA17= 0x4000180Eu, /* From scb[7].tr_tx_req to cpuss.dw1_tr_in[22] */
CY_TR_MUX_TR_INV_DISABLE, // do not invert
TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE,
// TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL,
1u); // dbg_frz_en
SCB setup
cy_stc_scb_uart_config_t g_stc_uart_config = {
.uartMode = CY_SCB_UART_STANDARD,
...
.rtsRxFifoLevel = 0,
.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
.breakWidth = 0,
.rxFifoTriggerLevel = 0,
.rxFifoIntEnableMask = E_UART_RX_INTR_FACTER,
.txFifoTriggerLevel = 2, // 126, // 0, Test: set trigger level to nearly empty buffer.
.txFifoIntEnableMask = E_UART_TX_INTR_FACTER // set to CY_SCB_UART_TX_TRIGGER | CY_SCB_UART_TX_DONE
};
Thank you for any help!
