Hi YSJE_3566666,
the CYT2B95CAS is equipped with a single CM4F core and CM0+.
Let's neglect the CM0+ and make an estimation of the CM4F. Maximum clock frequency is 160 MHz.
According to ARM the CM4F-core has a performance of 1.26 / 1.67 / 3.65 DMIPS/MHz,
with the first result complying to all of the “ground rules” laid out in the Dhrystone documentation, the second using inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All results were computed with the original (K and R) v2.1 of Dhrystone and Arm Compiler 6.17. (Check developer.arm.com/Processors/Cortex-M4).
If you do the math with the clock frequency you get a max-value that does not include wait states for memory access.
In the meantime I made my own tests with the Dhrystone algorithm from github („benchmark dhrystone master“) and a starter kit from Infineon (CYTVII-B-E-SK with CYT2B75CAD).
I used
- IAR EWARM V8.42.1
- Dhrystone 2.1
- Strcmp() from the standard library
- CYT2B75CAD running @ 160 MHz
- A TCPWM timer for time measurement
- Default settings for cache employment (cache enabled)
The CYT2B75CAD uses
- 1 flash memory access waitstate
- 8 kB internal instruction cache
My results with the CYT2B75CAD on the starterkit are
178771 Dhrystones/s equivalent to 102 DMIPS with optimizations set to „low“ (out-of-the-box setting of IAR), see screenshot 1
Screenshot 1
396039 Dhrystones/s eqivalent to 225 DMIPS with optimizations set to „high“ for speed, see screenshot 2
Screenshot 2
I would expect the same results with CYT2B9.
Hi YSJE_3566666,
the CYT2B95CAS is equipped with a single CM4F core and CM0+.
Let's neglect the CM0+ and make an estimation of the CM4F. Maximum clock frequency is 160 MHz.
According to ARM the CM4F-core has a performance of 1.26 / 1.67 / 3.65 DMIPS/MHz,
with the first result complying to all of the “ground rules” laid out in the Dhrystone documentation, the second using inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All results were computed with the original (K and R) v2.1 of Dhrystone and Arm Compiler 6.17. (Check developer.arm.com/Processors/Cortex-M4).
If you do the math with the clock frequency you get a max-value that does not include wait states for memory access.
In the meantime I made my own tests with the Dhrystone algorithm from github („benchmark dhrystone master“) and a starter kit from Infineon (CYTVII-B-E-SK with CYT2B75CAD).
I used
- IAR EWARM V8.42.1
- Dhrystone 2.1
- Strcmp() from the standard library
- CYT2B75CAD running @ 160 MHz
- A TCPWM timer for time measurement
- Default settings for cache employment (cache enabled)
The CYT2B75CAD uses
- 1 flash memory access waitstate
- 8 kB internal instruction cache
My results with the CYT2B75CAD on the starterkit are
178771 Dhrystones/s equivalent to 102 DMIPS with optimizations set to „low“ (out-of-the-box setting of IAR), see screenshot 1
Screenshot 1
396039 Dhrystones/s eqivalent to 225 DMIPS with optimizations set to „high“ for speed, see screenshot 2
Screenshot 2
I would expect the same results with CYT2B9.
