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TRAVEO™ T2G Forum Discussions

Nitesh_garg
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First reply posted First question asked Welcome!

Hi,

 

I'm trying to communicate M0 and M7 core via  IPC using shared memory defined at M7. The address of this memory I pass thorough the IPC data register.

IN round 1, I observe the correct data is read from M0.

For round 2 I updated the data at same memory location but this time also m0 is reading the same data at same memory location which it read in round 1. 

My observation is when same memory is read at M7 via GHS it shows a different data as compared to the data read for same location at M0 via GHS.

 

Please suggest and help!

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4 Replies
Pranith
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Hi @Nitesh_garg ,

Could you explain when you update the memory with the new data? Is the memory protected? Do you update the data after you acquire the IPC?

Can you provide a code snippet?

You could have a look at this thread: https://community.cypress.com/t5/Traveo-II/Protect-two-variables-using-IPC/td-p/268699

Regards,

@Pranith 

 

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Nitesh_garg
Level 1
Level 1
First reply posted First question asked Welcome!

@Pranith 

I'm updating the memory before acquiring  the lock. There is no memory protection implemented as of now.

Also Yesterday I enable clear SRAM option in Linker and since then even round 1 is also failing.

From you link it seems I should update shared memory after lock acquire.  I will try that too today. Let me know if there is any other suggestion.

Regards

Nitesh Garg

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Hi @Pranith ,

I tried updating the shared storage after Acquire, Unfortunately this is not helpful!

Regards,

Nitesh Garg 

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Pranith
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Moderator
100 sign-ins 50 sign-ins 25 replies posted

Hi,

Could you refer to the IPC example from the latest sample driver library:
https://www.cypress.com/documentation/software-and-drivers/traveo-ii-sample-driver-library

Can you provide a snippet of your code?

Regards,

@Pranith 

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