- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello.
I wish to know if the TRAVEO II supports the Pulse Per Second(PPS) pin of ethernet AVB.
Thanks and Best regards.
Glenn.
Solved! Go to Solution.
- Labels:
-
TRAVEO™ T2G
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Glenn,
In continuation of last reply, below are more findings :
- Regarding ETHx_ETH_TSU_TIMER_CMP_VAL pin:
This signal is asserted high when the upper 70 bits of TSU timer count value are equal to programmed comparison value defined by the following MMIO registers.
tsu_nsec_cmp[21:0]
tsu_sec_cmp[31:0]
tsu_msb_sec_cmp[15:0] - Regarding supporting the Pulse Per Second(PPS) pin :
This IP does not support PPS only by HW, because ETHx_ETH_TSU_TIMER_CMP_VAL pin signal triggers only once.
However, if SW change the programmed comparison value after ETHx_ETH_TSU_TIMER_CMP_VAL is asserted, ETHx_ETH_TSU_TIMER_CMP_VAL pin can be asserted every fixed period.
If this behavior is fulfilled PPS requirement, it can be used as PPS pin.
Thank you.
Regards,
Apurva
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello.
I means the AVB PPS Pulse Output pin.
It is for checking the AVB gPTP synchronization.
Thanks and Best regards.
Glenn.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello
And, Could you explained about ETHx_ETH_TSU_TIMER_CMP_VAL pin?
Thanks and Best regards.
Glenn.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Glenn,
In continuation of last reply, below are more findings :
- Regarding ETHx_ETH_TSU_TIMER_CMP_VAL pin:
This signal is asserted high when the upper 70 bits of TSU timer count value are equal to programmed comparison value defined by the following MMIO registers.
tsu_nsec_cmp[21:0]
tsu_sec_cmp[31:0]
tsu_msb_sec_cmp[15:0] - Regarding supporting the Pulse Per Second(PPS) pin :
This IP does not support PPS only by HW, because ETHx_ETH_TSU_TIMER_CMP_VAL pin signal triggers only once.
However, if SW change the programmed comparison value after ETHx_ETH_TSU_TIMER_CMP_VAL is asserted, ETHx_ETH_TSU_TIMER_CMP_VAL pin can be asserted every fixed period.
If this behavior is fulfilled PPS requirement, it can be used as PPS pin.
Thank you.
Regards,
Apurva
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Glenn,
As per initial analysis, It is observed that there is no specific Pulse Per Second(PPS) output pin of ethernet AVB.
And ETHx_ETH_TSU_TIMER_CMP_VAL pin is used as "Ethernet time stamp unit timer compare indication line".
I will look more and update you accordingly.
Thank you.
Regards,
Apurva