SROM operation timeout with systick on CM0+

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Kyo
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Hello,

my software design performs Flash erase operation on CM4 kernel and Systick based IO inversion operation on CM0+ kernel, I have encountered a phenomenon that when I remove the initialization code of Systick on CM0+ kernel, Flash erase operation on CM4 kernel can be ended normally (IPC can get SROM erase operation "unlocked", i.e. completed). However, when the initialization code of Systick is executed on CM0+ kernel, it fails (IPC cannot get the SROM erase operation "unlocked").

What is the possible reason for this.

Thanks,

Best Regards

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Jimmy_L
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你好,

默认情况下CM0+IRQ0的优先级为1,而systick的优先级可能为0,所以会导致IPC lock直至timeout的情况。您可以试试把CM0+IRQ0的优先级设为0,把systick的优先级设为3,看看还有没有问题。

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Kyo
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好像论坛中可以用中文提问。。。请让我直接用中文补充一下细节。

  • 芯片是CYT2B9
  • 使用SDL驱动
  • CM4中的Flash操作使用的是Blocking模式
  • 问题是,正常在“blocking”的情况下,Flash擦写操作中SDL中它将轮询直到 Cy_IPC_Drv_IsLockAcquired() 返回“false”。但当CM0中存在Systick的初始化代码时,Cy_IPC_Drv_IsLockAcquired()会等不到 返回“false”,最后会发生Timeout。

抱歉没有办法提供基于SDL sample的最小代码,但是如果有其他需要补充的细节请联系我。谢谢!

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Jimmy_L
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250 replies posted 250 sign-ins 50 solutions authored

你好,

默认情况下CM0+IRQ0的优先级为1,而systick的优先级可能为0,所以会导致IPC lock直至timeout的情况。您可以试试把CM0+IRQ0的优先级设为0,把systick的优先级设为3,看看还有没有问题。

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Kyo
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你好,感谢回复,

我这边有其他优先事务,等过两天之后确认一下您提供的方法,如果可行会回来反馈。

谢谢

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Kyo
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你好 按照您提供的方法尝试了一下,是有效果的。

请问为什么systick的优先级高于CM0+IRQ0时会导致IPC lock直至timeout呢?因为按照一般的理解,即使systick中断优先级很高,但是总会有动作的间隙可以去执行比它优先级低的CM0+IRQ0中断请求。所以不是很理解为什么会IPC lock直至timeout。能稍微深入的解释一下吗?

另外,如果总结的话,关于IPC相关的中断(比如Flash相关的操作),可以理解为只要有比它优先级高的中断存在,那IPC的中断一定会得不到响应(比如lock直至timeout),是吗?

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Jimmy_L
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250 replies posted 250 sign-ins 50 solutions authored

你好,

因为中断会根据优先级来执行,如果此时systick和flash操作的中断同时到来,按照默认配置,那么是一定会先执行优先级高的thread,也就是systick,而当systick中断比较频繁,就会导致flash操作的中断长时间得不到相应造成timeout。

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Kyo
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十分感谢您的回复。👍

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