SRAM1 and SRAM2 memory value retains even after power mode is turned off

[eswaran]

Hello Experts,

                           I am working on deepsleep mode for traveo ii and I am trying to power off the SRAM 1 and 2. Before powering off I have just written a data under SRAM 1 and 2 memory to check whether the contents are lost after power off. But I observed that the contents written still remains even though the power for the particular SRAM is configured off.

Can you please support me on this. Thanks.

[Kavya_B · Accepted solution]

Hello @eswaran ,

Could you please configure 'PWR_MODE' fields in registers CPUSS_RAM1_PWR_CTL and CPUSS_RAM2_PWR_CTL registers to 0x0 (OFF) before transitioning to deep sleep mode and check the behavior?

Please refer to section 'RAM Retention Configuration' in Architecture TRM document for details.

Thanks,

Kavya

[eswaran]

Hello @Kavya_B 

I have configured the power mode as 0 and proceeded but still the value retains there in that particular address. I have done this for RAM2_PWR_CTL. I 

[Kavya_B]

Hello @eswaran ,

Do you see that only at address 0x28040000 the value is getting retained even if you power off (CPUSS_RAM2_PWR_CTL.PWR_MODE = 0), but no other location in SRAM1 or SRAM2 do not retain the data with this configuration? Please clarify.

Thanks,

Kavya

[chey]

If data cache is enabled, you might be looking at cache contents and not actual SRAM contents