SRAM interface - ECC Error Injection mechanism

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LorenzoCalzolar
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Hello,

I'm asking support for the ECC Error Injection into SRAM, in order to implement a RAM test for a safety function. The chapter 10.3.3 of Technical Reference Manual report the following instruction, to generate a fault:

The fault reporting structure for ECC faults can be debugged through an SRAM controller ECC parity injection mechanism.
This mechanism functions as follows:
■ ECC injection is enabled through CPUSS_RAMx_CTL0.ECC_INJ_EN (for SRAM controller x).
■ A word address is specified by CPUSS_ECC_CTL.WORD_ADDR[23:0]
(CPUSS_ECC_CTL.WORD_ADDR = (0x00FFFFFF & (RAM_TEST_ADDRESS>>2))).
■ A 8-bit parity is specified by CPUSS_ECC_CTL.PARITY[7:0].
When a write transfer to the specified word address is performed, the ECC parity generation uses the specified 8-bit parity,
rather than the calculated parity. The data still originates from the bus transfer. Any access size can be used to inject parity.

So, based on these indications, i define a RamTest variable, and write its address on CPUSS_ECC_CTL.WORD_ADDR (where to inject the error):

CYREG_CPUSS_ECC_CTL->stcField.u24WORD_ADDR = (0x01FFFFFF & ((uint32_t)&u64_VfSelfTest_RAMTest>>2));

write a parity to inject as an error:

CYREG_CPUSS_ECC_CTL->stcField.u8PARITY = 0x5A;

enable the injection:

CYREG_CPUSS_RAM0_CTL0->stcField.u1ECC_INJ_EN = 1u;

and at least write and read the variables, to generate error, wich should be reported by fault reporting structure (FAULT_STRUCT_STATUS, Description: Fault status, Address: 0x4021000C). But at the moment the FAULT_STRUCTx_STATUS.VALID still remains set to ‘0’ (no fault) and no fault interrput is generate.

What is wrong?

Thanks for the support

 

 

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Hi LorenzoCalzolar,

Please try the attached example project based on SDL 7.5.0 (I tested on CYT4BF device on CM7 core, but it should work on CYT3DL also. You may need to modify a little for port-pin mapping depending on your board however).

Regards,

Ashish

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Ashish
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25 likes received 50 solutions authored 100 replies posted

Hi LorenzoCalzolar,

Can you please tell the part number of the device (is it TVII- BE or BH product?). I think you should shift by 3 (RAM_TEST_ADDRESS>>3) for body-high device (CYT3B/4B). As far as your use case is concerned (ECC error injection for SRAM)- there is already example in the SDL- you can refer to that for your reference.

Thanks,

Ashish

 
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Hi Ashish,

the part number of device is CY3DL.

Thanks for the support

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Sorry, where I could find example?

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Hi LorenzoCalzolar,

Please try the attached example project based on SDL 7.5.0 (I tested on CYT4BF device on CM7 core, but it should work on CYT3DL also. You may need to modify a little for port-pin mapping depending on your board however).

Regards,

Ashish

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