# SRAM ECC Parity generation by software For Trave 2G CYT3BB

## SRAM ECC Parity generation by software For Trave 2G CYT3BB

Level 1
Level 1

In SRAM ECC Parity Generation, there is an algorithm to generate parity bits using the software.

The Algorithm

10.3.4 ECC Parity Generation by Software
To inject the ECC error for fault generation, ECC parity must be generated by software. Follow this procedure to generate
8-bit ECC parity.
CODEWORD_SW[127:0] = {128 {1'b0}};
CODEWORD_SW[63:0] = ACTUALWORD[63:0];
Note: RAM_SIZE is size of RAMx, where “x” is the RAM unit number.
ECC_P0_SW = 128b00000001_10111111_10111011_01110101_10111110_00111010_01110010_11011100_
01000100_10000100_01001010_10001000_10010101_00101010_10101101_01011011;
ECC_P1_SW = 128b00000010_11011111_01110110_11111001_11011101_10011001_10111001_01110001_
00010001_00001000_10010011_00010001_00100110_10110011_00110110_01101101;
ECC_P2_SW = 128b00000100_11101111_11001111_10011111_10011010_11010101_11001110_10010111_
00000110_00010001_00011100_00100010_00111000_11000011_11000111_10001110;
ECC_P3_SW = 128b00001000_11110111_11101100_11110110_11101101_01100111_01001110_01101100_
10011000_00100001_11100000_01000011_11000000_11111100_00000111_11110000;
ECC_P4_SW = 128b00010000_11111011_01111011_10101111_01101011_10100110_10110101_10100110_
11100000_00111110_00000000_01111100_00000000_11111111_11111000_00000000;
ECC_P5_SW = 128b00100000_11111101_10110111_11001110_11110011_01101100_10101011_01011011_
11111111_11000000_00000000_01111111_11111111_00000000_00000000_00000000;
ECC_P6_SW = 128b01000000_11111110_11011101_01111011_01110100_11011011_01010101_10101011_
11111111_11111111_11111111_10000000_00000000_00000000_00000000_00000000;
ECC_P7_SW = 128b10000000_01111111_00000000_00000000_00000111_11111111_11111111_11111111_
11010100_01000010_00100101_10000100_01001011_10100110_01011100_10110111;
As shown here, Reduction XOR of the ANDed result of CODEWORD_SW[127:0] and respective ECC constants will give a
single parity bit.
parity[0] = ^ (CW_SW[127:0] & ECC_P0_SW)
parity[1] = ^ (CW_SW[127:0] & ECC_P1_SW)

parity[7] = ^ (CW_SW[127:0] & ECC_P7_SW)
Parity [6:0] gives seven bits parity for 32 bits ACTUALWORD [127:0].

The Question is, shall we implement this procedure in the SRAM_ECC Test? or use another parity bits.

1 Solution

## Re: SRAM ECC Parity generation by software For Trave 2G CYT3BB

Moderator
Moderator

Hello @youssefmaaty

• We don’t have any code example or any tool for parity generation logic.
• The user itself has to implement the SW logic themselves and find out the right parity value
• Once the user knows the correct parity value for a particular address location and data, then the user can flip bits to know 1-bit and 2-bit parity values for ECC error injection testing

Thanks & Regards

Abhishek Kulkarni

## Re: SRAM ECC Parity generation by software For Trave 2G CYT3BB

Moderator
Moderator

Hello @youssefmaaty

• We don’t have any code example or any tool for parity generation logic.
• The user itself has to implement the SW logic themselves and find out the right parity value
• Once the user knows the correct parity value for a particular address location and data, then the user can flip bits to know 1-bit and 2-bit parity values for ECC error injection testing

Thanks & Regards

Abhishek Kulkarni