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taegyunahn
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25 replies posted First comment on blog First solution authored

Hi.

I am using CYT4BFCCJ.

And tested with CYTVII-B-H-8M-320-CPU and SDL v8.0.0(examples/scb/spi/High_level_driver/api)

 

After setting up the SPI master mode, I confirmed that the SCB0 SPI SELECT pin status remained High level in Active mode.

And I confirmed that the SCB0 SPI SELECT pin state drops to Low level in DeepSleep mode.

However, SCB1(or n) SPI SELECT pin status remained High level in DeepSleep mode. (Does not drop to low level)

- SCB0 PortPin : P1_3_SCB0_SPI_SELECT0, P2_0_SCB0_SPI_SELECT1, P2_1_SCB0_SPI_SELECT2, P2_2_SCB0_SPI_SELECT3

- SCB1 PortPin : P18_3_SCB1_SPI_SELECT0, P18_4_SCB1_SPI_SELECT1, P18_5_SCB1_SPI_SELECT2, P18_6_SCB1_SPI_SELECT3

 

Q : Why does the SCB0 SPI SELECT pin state drop to Low level in DeepSleep mode?
(Sleep mode retains the SCB0 SPI SELECT pin state at high level)

I know that SCB0 can be used in DeepSleep mode.

taegyunahn_0-1703755861232.png

taegyunahn_1-1703755891171.png

 

Thank & Best regards

taegyunahn

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9 Replies
Imam_M
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50 replies posted 10 likes received 10 solutions authored

Hi @taegyunahn,

In my side, I change the line below from CY_SCB_SPI_SLAVE to CY_SCB_SPI_MASTER and add another macro for testing in deepsleep mode (in the image below).
Imam_M_0-1703836610184.png

The following image is logic analyzer log result for my test.
Imam_M_1-1703837483480.png
Channel 0 -- SCB0_SELECT0
Channel 1 -- Hibernate Button

In the image, as you can see once I activate the button, from your explanation it should goes to LOW. But in my side, SCB0_SELECT0 still in high condition. 

Kindly could you inform what you have been change in our provided SDL example? I believe by providing that will help us analyze your project. Thank you.

taegyunahn
Level 4
Level 4
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25 replies posted First comment on blog First solution authored

Hi @Imam_M 

Are cm0p, cm7_0, and cm7_1 all set to deepsleep mode? (debugger not connection)

Doesn't the scb0_spi_selecet pin drop to low level then?

Thank you.

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taegyunahn
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Level 4
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25 replies posted First comment on blog First solution authored

Hi @Imam_M.

I am attaching tested code based on SDL v8.0.0(examples/scb/spi/High_level_driver/api).

cm7_0 performs SPI pin configuration and SPI Init and enters DeepSleep mode after a 3-second wait time.

cm0p, cm7_1 enter DeepSleep mode immediately.

When all cores enter DeepSleep mode, the SCB0_SPI_SELECT pin drops to low level.

You can test with SCB0 and SCB1 by modifying the attached bb_bsp_tviibh8m.h file as shown below.

taegyunahn_0-1704190667997.png

 

Thanks & Best regards

taegyunahn.

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Imam_M
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50 replies posted 10 likes received 10 solutions authored

Hi @taegyunahn,

Thank you for your confirmation and clarification.

Are cm0p, cm7_0, and cm7_1 all set to deepsleep mode?
Yes, we tested the mentioned examples on our side by putting CM0p, CM7_0, and CM7_1 in deep-sleep mode. Then we still got the same result that the SCB0_SELECT0 Line still is in HIGH.

Regarding the attached image you put in the previous response, kindly could you check why SEL0 HSIOM is to P0_3? in my understanding, it should be P1_3.
Because as you can see in the image you shown, seems like there's a mismatch connection between port, pin, and hsiom there. Thank you.


Sincerely,
IM

taegyunahn
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25 replies posted First comment on blog First solution authored

Hi @Imam_M .

Thank you for answer.

I modified it to P1_3_SCB0_SPI_SELECT0(HSIOM=30) in my test code.

However, since it is the same HSIOM number, there does not seem to be any difference in operation

 

When entering DeepSleep with CM0P, CM7_0, CM7_1, and Debugger disconnected, all SCB0_SPI_SELECT(0~3) pin drop to Low level.(Please refer to the image below.)

taegyunahn_0-1704281826909.png

I conducted the test using CYTVII-B-H-8M-320-CPU EVB, and modified the EVB's HW for accurate testing.
- SCB0_SPI_SEL1: Remove R256
- SCB0_SPI_SEL3: Remove R121

Additionally, I confirmed that the same problem occurs in CYT2B9. (Tested with CYTVII-B-E-176-SO, CYTVII-B-E-BB EVB)

The same problem is occurring in both TVII-B-E and TVII-B-H products.

 

Q1. Please check again whether the all SCB0_SPI_SELECT(0~3) pin drops to low level when entering DeepSleep mode. You can easily test it with the code I attached.

(CM0P, CM7_0, CM7_1 Deepsleep mode, Debugger disconnect)

 

Q2. The other SCBn keeps the SELECT pin HIGH when entering deepsleep mode.

I understand that only SCB0 can be used in DeepSleep mode. I wonder if that is relevant?

 

Please check the above information.

taegyunahn.

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Imam_M
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50 replies posted 10 likes received 10 solutions authored

Hi @taegyunahn,

Apologies, after double-checking my board, previously my board is connected to something else that drives it to be high. And yes, now I am able to reproduce your issue.

Regarding SPI in deep sleep mode, apologies, I was missing the following information from TRM.

Imam_M_0-1704338939329.png
(Source: T2G Body High TRM, Rev. *G pg 299)

Based on that information, only SPI slave mode available in deepsleep mode. Then this means select0 drives to low because in t2g becomes slave mode and in slave mode, select pin drive mode is in high-z. Apologies again for the confusion and hope this answers your query. Thank you.

Sincerely,
IM

taegyunahn
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25 replies posted First comment on blog First solution authored

Hi @Imam_M .

Thank you for answer.

 

I have additional questions as follows.

Q1) What you mentioned is that when SCB0 SPI is set to Master mode in Active mode, when it enters DeepSleep mode, does it change to Slave mode? So, is it correct that the SELECT pin drive mode changes to high-z and drops to low level?

[SPI MASTER I/O PAD]

taegyunahn_2-1704357118492.png

[SPI SLAVE I/O PAD]

taegyunahn_1-1704357078898.png

Q2) Are there more port pins that may cause differences in operation in DeepSleep mode? (ex. SCB0_SPI_SELECT pin) Please refer to the table below.

taegyunahn_0-1704356861144.png

 

Thanks.

taegyunahn.

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Imam_M
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50 replies posted 10 likes received 10 solutions authored

Hi @taegyunahn,

Q1) Yes, your understanding is correct. But if you're planning to activate SPI SCB in deepsleep mode, I suggest you to set this SCB SPI0 as slave from the beginning.

Q2) In deepsleep, only SCB I2C and SPI are affected (both only works as slave-mode). I think the mentioned table already explain information for other peripherals in deepsleep.

I hope this helps your query. Thank you.

Sincerely,
IM

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taegyunahn
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25 replies posted First comment on blog First solution authored

Hi @Imam_M 

Thank you for answer.

I am currently using SCB0 SPI in Master mode and have no plans to use it in Slave mode. The problem is that the pin state changes in DeepSleep mode.

 

Unfortunately, it doesn't seem to automatically switch from Active to Master mode to DeepSleep to Slave mode.
If that is correct, all SPI registers that must be set to operate in Slave mode will have to be changed in Deepsleep.

Q1) Can you please confirm again whether SCB0 operates as Master in Active mode and automatically switches to Slave mode when entering DeepSleep?
Q2) If it is true that SCB0 automatically switches from Deepsleep to Slave mode and operates, what registers are changed?

Thank you.
taegyunahn.

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