Question about PLL Clock Jitter imact

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WonjinHan
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Dears.

 

Now I’m evaluating CAN clock tolerance and found the following link

Link : PLL Clock Jitter Impact on CAN Precision in TRAVEO... - Infineon Developer Community

 

I understood that each “For 125ns(SID342), 500ns(SID343), 1000ns(SID344), 10000ns(SID345)” in Datasheet means data speed.

In the link, it is calculated for CAN 1Mbps use case, so I believe that PLL jitter should be 0.5ns not 0.75ns.

Because “For 1000ns” means 1MHz. Could you review my understanding is correct ?

PLL_JITTER.png

 

 

Best regards,

Kevin Han.

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Pranith
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Hello @WonjinHan 

Your understanding is correct. SID344 would apply. We will initiate a change to the KBA.

Regards

WonjinHan
Level 5
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Hello Pranith.

Thank you for your answer and good to hear that. 

 

Best regards, 

Kevin Han. 

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