Parallel access of DATA flash or Code flash in Traveo II

[Venkatesh]

Hi All,

Will there be any issue in erasing a code flash or writing to code flash region.
While your application is running in a different code flash region.



Is there any document which talks about parallel access of data and code flash in Traveo II.

[Kavya_B · Accepted solution]

Hello @Venkatesh ,

In Traveo II controllers, 'reading while programming/erasing' feature is supported in the granularity of Flash logical banks.

Meaning, reading from one flash logical bank while programming/erasing on other flash logical bank is supported in Traveo II. However, reading and writing on same logical bank is not supported and will lead to issue.

User can configure single or dual bank modes for code or work flash. FLASHC_FLASH_CTL.MAIN_BANK_MODE register configuration bit decides it for code flash and FLASHC_FLASH_CTL.WORK_BANK_MODE for work flash.

Please refer to 'Flash Geometry' subsections under chapters 'Code Flash' as well as 'Work Flash' in Traveo II architecture TRM (Document No. 002-19314 Rev. *H - Body Entry Architecture TRM) for more details.

You may also consider referring to application note 'AN220242 - Flash accessing procedure for TRAVEO™ T2G
family'. Link for the same is mentioned below:

https://www.infineon.com/dgdl/Infineon-AN220242_Flash_Accessing_Procedure_for_Traveo_II_Family-Appli....

Thanks,

Kavya