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ChiragP
Level 1
Level 1
5 sign-ins First question asked Welcome!

Hello, 

I'm trying to find the delay between when clock is presented at Traveo II's input Clock pin (SCB4 P10.2) until it puts out data on its MISO output pin P10.0 (assume Traveo II is a SPI Slave). 

I see 62ns max inside CYT2BL7BAAQ0AZSGS datasheet for internal-clocked mode. Not sure what internal clocked mode means. 

ChiragP_0-1692129582901.png

Thanks

Chirag

 

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1 Solution
Reza_A
Moderator
Moderator
Moderator
25 solutions authored 10 likes given 50 replies posted

Hi @ChiragP,

The SID207 that you mentioned is for internal-clocked mode just as you mentioned. For external-clocked mode, which is typically used in a SPI slave where the SPI receives the clock input from the CLK pin, kindly refer to SID222 and please check if it's the specification that you require.

Randriad_0-1692157980733.png

Kindly also refer to the Architecture TRM sub-section 24.3.2 to read the explanation on the SCB clocking modes.

Randriad_1-1692157993740.png

I hope this helps.

Best regards.

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1 Reply
Reza_A
Moderator
Moderator
Moderator
25 solutions authored 10 likes given 50 replies posted

Hi @ChiragP,

The SID207 that you mentioned is for internal-clocked mode just as you mentioned. For external-clocked mode, which is typically used in a SPI slave where the SPI receives the clock input from the CLK pin, kindly refer to SID222 and please check if it's the specification that you require.

Randriad_0-1692157980733.png

Kindly also refer to the Architecture TRM sub-section 24.3.2 to read the explanation on the SCB clocking modes.

Randriad_1-1692157993740.png

I hope this helps.

Best regards.