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uids9644
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When we configurate the LIN_TX as strong, the LIN bus spike error always occur before break part is send.

But we configurate the LIN_TX as pull-up, no LIN bus spike error. 

We don't know why.

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1 Solution
TechSW
Employee
Employee
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Hello,
Port Output Drive Strength:
"Strong" is just a push & pull output stage. The driver strength depends on your selection. 

GPIO_PRTx_CFG_OUT:DRIVE_SELy
GPIO_PRTx_CFG_OUT:SLOWy

Please use for your testing setting:
DRIVE_SEL = 0 (strongest driver strength) and SLOW = 0 

Try your LIN_TX setting for GPIO_PRTx_OUT = '1', before you configure the port pin and the LIN IP. Even when you want to use the LIN IP function and not as GPIO, because this is the idle level for LIN signal.
Maybe the slow falling edge comes, because the LIN IP is disabled in between and therefore no active level is driven and you see a floating levels and its discharging due to leakage. When the LIN is re-enabled and the pin is actively driven with his driver strength to logic "high".
Note: OUT_EN itself is an chip internal signal and cannot be monitored by the user. But it should be either connected by enabling the LIN_EN or shortly before the transmission is started.
Best Regards

 

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TechSW
Employee
Employee
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Hello,

 

  1. Do you use the dedicated LIN IP in Traveo T2G?
  2. Did you configure both pins correctly TX and RX according to the SW example?
  3. Do you mean the LIN BUS ERROR? If yes, this flag only occurs, when the RX input is different from the TX signal. Did you check both signals externally on the oscilloscope? Maybe the LIN transceiver is "off".
  4. Did you check, when the error flag is set on the oscilloscope vs the LIN signals?
  5. Do you configure the IO Pins after or before enabling the LIN IP?
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Maybe you could understand this LIN spike error from below oscilloscope pic.

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MCU used is CYT2B95CAS and LIN trans is TJA1029TK from NXP.

The pins are as below: LIN_TX -- P12.3 (LIN6_TX), LIN_RX -- P12.2 (LIN6_RX) and LIN_EN -- P12.1 (LIN6_EN)

 

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TechSW
Employee
Employee
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Hello,

the root cause is not clear to myself.

Can you provide feedback to the still open items, please?

  1. Did you configure both pins correctly TX and RX according to the SW example?
  2. Did you check, when the error flag is set on the oscilloscope vs the LIN signals?
  3. Do you configure the IO Pins after or before enabling the LIN IP?
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  1. Did you configure both pins correctly TX and RX according to the SW example? 
    • Yes!  You could find the LIN normal frames in CANoe trace. And LIN_TX and LIN_RX are configurated correctly. 
  2. Did you check, when the error flag is set on the oscilloscope vs the LIN signals?
    • I have updated the oscilloscope pics included LIN_TX, LIN_EN, LIN_RX and LIN as above.
  3. Do you configure the IO Pins after or before enabling the LIN IP?
    • I have checked the IO pins are configurated before LIN IP enabled.
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TechSW
Employee
Employee
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Hello,

please check following:

1. Did you check the timing in the debugger tool, if you skip some LIN activities? Means two consecutive TX commands (e.g. TX_HEADER) and one of them is canceled for any reason.

2. Adding IO pin toggling to the LIN signal on the scope could help, when executing TX commands.

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hello TechSW

This is just important point. You could fine scope pic that "LIN spike error" -- the falling edge is slow, while the rising edge is steep. This can not be explained.

And if I change LIN_TX drive mode from strong to Resistive Pull Up , the issue disappears. This can not be  also explained.

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TechSW
Employee
Employee
First like received First question asked First like given

Hello,
Port Output Drive Strength:
"Strong" is just a push & pull output stage. The driver strength depends on your selection. 

GPIO_PRTx_CFG_OUT:DRIVE_SELy
GPIO_PRTx_CFG_OUT:SLOWy

Please use for your testing setting:
DRIVE_SEL = 0 (strongest driver strength) and SLOW = 0 

Try your LIN_TX setting for GPIO_PRTx_OUT = '1', before you configure the port pin and the LIN IP. Even when you want to use the LIN IP function and not as GPIO, because this is the idle level for LIN signal.
Maybe the slow falling edge comes, because the LIN IP is disabled in between and therefore no active level is driven and you see a floating levels and its discharging due to leakage. When the LIN is re-enabled and the pin is actively driven with his driver strength to logic "high".
Note: OUT_EN itself is an chip internal signal and cannot be monitored by the user. But it should be either connected by enabling the LIN_EN or shortly before the transmission is started.
Best Regards

 

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I also would like to get info about OUT_EN. It is not user configurable. 

In the debugger tool,  which register could I monitor to response OUT_EN?

And what changes will affect OUT_EN changes?

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uids9644
Level 1
Level 1
5 questions asked 10 sign-ins First like received

Anyone could help to solve this issue?

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