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TRAVEO™ T2G Forum Discussions

KaKo_4074056
Level 4
50 sign-ins 25 sign-ins 10 replies posted
Level 4

Hi,

There seems to be a difference in the initial state of the input buffer between the following two. Which one is correct?

2.1. What is the status of unused GPIO pins?
The default mode is High-Z, input buffer is enabled, and no internal pull-up/down resister connected.
https://community.infineon.com/t5/Knowledge-Base-Articles/Traveo-II-Automotive-Body-Controller-FAQ-G...

T2G Body Entry Arch TRM (002-19314 Rev. *H)
22.6.1 Drive Modes -> High-Impedance
High-impedance drive mode with input buffer disabled is also the default pin reset state.

Best regards,

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1 Solution
KumarAP
Moderator
Moderator 10 solutions authored First like given 25 sign-ins
Moderator

Hello,

The correct info is :

T2G Body Entry Arch TRM (002-19314 Rev. *H)
22.6.1 Drive Modes -> High-Impedance
High-impedance drive mode with input buffer disabled is also the default pin reset state.

 

Also, we will update the same information in below mentioned KBA.

https://community.infineon.com/t5/Knowledge-Base-Articles/Traveo-II-Automotive-Body-Controller-FAQ-G...

 

Thank you.

Regards,

Apurva

View solution in original post

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2 Replies
KumarAP
Moderator
Moderator 10 solutions authored First like given 25 sign-ins
Moderator

Hello,

The correct info is :

T2G Body Entry Arch TRM (002-19314 Rev. *H)
22.6.1 Drive Modes -> High-Impedance
High-impedance drive mode with input buffer disabled is also the default pin reset state.

 

Also, we will update the same information in below mentioned KBA.

https://community.infineon.com/t5/Knowledge-Base-Articles/Traveo-II-Automotive-Body-Controller-FAQ-G...

 

Thank you.

Regards,

Apurva

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JJack
Level 4
10 likes received 25 replies posted 10 solutions authored
Level 4

Hello Kako_4074056,

for your reference and understanding of KumarAP's answer please have a look at the T2G's register TRM, chapter GPIO, register GPIO_PRT_CFG. After Reset the default value of this register ist 0x0. This means thal all the bits IN_ENx are cleared to zero, too.

JJack_0-1657015604930.png

When IN_ENx == 0 then the input buffer is disabled. So, as KumarAP already pointed out, the default pin reset state is high-impedance with input buffer disabled.

 

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