I am using CYT4BF MCU which has one CM0+ core and two CM7 cores
I have two questions.. Please answer. Thanks.
1. In the datasheet, I saw like an IPC interrupt structure line is connected to all processors. How can configure a single IPC interrupt structure line specific to one core
2. It is possible to use same Interrupt structure for single IPC channel. For example, I want to communicate between CM0+ and CM7_0 core and, if I use IPC channel 4, Is it possible to configure both Int_Notify_4 and Int_Release_4 to INTR_Structure_3. If possible how to configure INTR_Structure_4 interrupt line to connect to both CM0+ and CM7_0.
Note: Please see the attached figure from datasheet, where IPC channel 1 is trying use INTR_Structure_2 for both Notify and Release
1. Any particular IPC channel can be acquired by any core by reading the IPC_STRUCTx_ACQUIRE register. If 'SUCCESS' field of this register returns a '1' it means that the particular IPC channel was successfully acquired. Now, once the channel is acquired, the interrupt can be configured by writing to the IPC_STRUCTx_NOTIFY register. The IPC_STRUCTx_NOTIFY register has eight INTR_NOTIFY[7:0] bits which correspond to the eight IPC interrupts. Setting any of the INTR_NOTIFY[7:0] bits in the IPC_STRUCTx_NOTIFY register also sets the corresponding NOTIFY[23:16] bit in the IPC_INTR_STRUCTx_INTR register and the interrupt is configured.
Let us consider you want to acquire IPC channel 0 and configure IPC interrupt 2. Then, you should first read the IPC_STRUCT0_ACQUIRE register. After acquiring the IPC channel 0 successfully, you should set the INTR_NOTIFY bit in the IPC_STRUCT0_NOTIFY register. This will set the NOTIFY bit in the IPC_INTR_STRUCT2_INTR register.
Hope this answers your question. You can also refer to the example provided in SDL. You can also refer to section '5 Communicating between CPUs' of the following application note - https://www.infineon.com/dgdl/Infineon-AN224432_Multi_Core_Handling_Guide_in_Traveo_II-ApplicationNo...
2. Your question is not completely clear to us. Could you please explain more clearly? Meanwhile, I am also checking internally on this.
1. In the diagram, at the bottom of INTR_X, it is mentioned that "Interrupt to Processors".
a. Does it mean it is connected to all the cores available?
b. How can we enable it to interrupt a particular core?
2. In the diagram, IPC channel 1 is trying use INTR_2 for both Notify and Release interrupts. Is it possible to use same Interrupt structure for single IPC channel? Here my doubt is, how does a single INTR interrupt can be able to interrupt say Core A(For Notify) and Core B(For Release).
To illustrate what Kavya just wrote:
1a) Yes, all system/peripheral interrupt request signals are split and fanned out to every core
1b) By standard interrupt handling procedure, just like for example an interrupt request from a GPIO. But you have to implement this twice: in the code for CM7_0 and in the code for CM7_1 because each core has its dedicated interrupt vector table and interrupt control registers. You also have to write two Interrupt Service routines. One in the code for CM7_0 and the other one in the source files for CM7_1. The linker will link them to the respective entries in the interrupt vector tables of the two different cores.
2) see Kavya's answer
Regarding your previous questions:
1) As listed in Table 'Peripheral Interrupt Assignments and Wake-up Sources' in the datasheet, all the IPC interrupt structures are nothing but system interrupt sources. By default, IPC interrupt structures are not linked to any specific core. User has to link the IPC interrupt structures to one or multiple cores based on the need.
Each core in Traveo II will have 8 CPU interrupts. Just like in case of any other system interrupts, IPC interrupt structure needs to be mapped to respective CPU interrupt IDs of one or more cores based on user requirements.
2) It is possible to use same IPC interrupt structure to 'Notify' and 'Release' from same IPC channel structure. In such case, the interrupt structure needs to be mapped to CPU interrupts of both the cores. Interrupt gets triggered on both the cores for either Notify or Release event. In the ISR routines, only relevant Notify/Release bits of Interrupt structure need to be checked, processed and cleared without altering the other bits. Note that in such cases, processing Notify events by both the cores and processing Release events by both the cores at the same time may lead to race conditions. As far as Notify and Release events are processed and cleared by two different cores, I think it should be possible.