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jthimmar
Level 1
Level 1
First reply posted 5 sign-ins First question asked

In our Project with Cypress controller , we have enabled dual bank configuration to support OTA update 

Before we jump to inactive region we check to see if the inactive region  has  a valid application.

In the use case when the inactive memory region is not flashed and we try to read the  4 bytes of data from application starting address. We occasionally get a hardfault exception.

Does this imply that we cannot read memory that has been erased?

How do we turn off the Hardfault exception?

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1 Solution
JJack
Level 5
Level 5
Associated Partner - Distributor Rutronik
5 questions asked 25 likes received 100 sign-ins

Hi Jthimmar,

according to Vector Informatik’s support note SN-IES-1-15, section 4.2, it is not allowed to perform a read operation on an erased area in Traveo2.

My guess is that the ECC check fails with more than 1 bit-error. This is because the correct ECC parity value is updated and stored only when the flash is written/programmed. After an erase data and parity do not match yet and your read operation triggers the ECC check.

You could try the following:

+ Temporarily disable the ECC check before test-reading the address in question. Do not forget to re-enable the ECC check afterwards.

Or

+ run a blank check before reading.

BR

JJack

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2 Replies
JJack
Level 5
Level 5
Associated Partner - Distributor Rutronik
5 questions asked 25 likes received 100 sign-ins

Hi Jthimmar,

according to Vector Informatik’s support note SN-IES-1-15, section 4.2, it is not allowed to perform a read operation on an erased area in Traveo2.

My guess is that the ECC check fails with more than 1 bit-error. This is because the correct ECC parity value is updated and stored only when the flash is written/programmed. After an erase data and parity do not match yet and your read operation triggers the ECC check.

You could try the following:

+ Temporarily disable the ECC check before test-reading the address in question. Do not forget to re-enable the ECC check afterwards.

Or

+ run a blank check before reading.

BR

JJack

Kavya_B
Moderator
Moderator
Moderator
10 likes given 25 solutions authored 5 likes given

Hello @jthimmar ,

I agree to the comments from @JJack . 2-bit (non-correctable) ECC error will lead to hard fault (if error silent bits in FLASHC_FLASH_CTL registers are kept as 0) in T2G controllers.

However, if the address read was from erased code flash then it is not expected to throw ECC errors where as  erased work flash addresses will do. The quick test suggested by @JJack  will help to check if non-correctable ECC errors reported from erased work flash is the cause for hard fault in your case.

Please let us know your test observations.

Regards,

Kavya

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