Currently we use CYT2B7 for our development. The data flash read is quite slow which impacts our device initialization time. Could you please suggest how to improve data flash read time?
could you please elaborate on this a little. Maybe you can give some figures what read access rate you expect and what you actually get. Which cpu core is doing the Reads? As can be seen in the inserted picture, flash access of CM0+ for example is using the "slow infrastructure" while CM4 is using the "fast infrastructure".