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Dears.
Now I’m taking the test with software logic analysis of Traveo II SDL 6.6.0 on CYTVII-B-E-176-SO.
In UART(115200Baud rate) clock part, I don’t understand the following code to configure the fractional divider.
uint64_t targetFreq = UART_OVERSAMPLING * boadrate; uint64_t sourceFreq_fp5 = ((uint64_t)sourceFreq << 5ull); uint32_t divSetting_fp5 = (uint32_t)(sourceFreq_fp5 / targetFreq); Cy_SysClk_PeriphSetFracDivider(CY_SYSCLK_DIV_24_5_BIT, 0ul, ((divSetting_fp5 & 0x1FFFFFE0ul) >> 5ul), (divSetting_fp5 & 0x0000001Ful)); |
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Could you give me your explanation or tips to clearly understand it?
Br,
WonjinHan.
Solved! Go to Solution.
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Dear all.
I clearly understood it from Architecture Technical Reference and Appliation Note as the following.
CLK_PERI Frequency = 80MHz
115200 * 8 = Input Clock = 921600
DIV24.5 = 80MHz / 921600 = 86.805
Fractional Divider
Integer : 86 , Fractional : 25
Thank you.
WonjinHan.
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Dear all.
I clearly understood it from Architecture Technical Reference and Appliation Note as the following.
CLK_PERI Frequency = 80MHz
115200 * 8 = Input Clock = 921600
DIV24.5 = 80MHz / 921600 = 86.805
Fractional Divider
Integer : 86 , Fractional : 25
Thank you.
WonjinHan.