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TRAVEO™ T2G Forum Discussions

Venkatesh
Level 1
10 sign-ins 5 questions asked 5 sign-ins
Level 1

Hello All,

In Traveo II can we reconfigure the PLL settings(CM4) after PLL is locked in CM0+.

 

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1 Solution
JJack
Level 4
10 likes received 25 replies posted 10 solutions authored
Level 4

Hi Venkatesh,

I guess you mean

Can the application processor (CM4) safely reconfigure the PLL which is in its own clockpath?

The register manual says "do not change settings while the PLL is enabled and connected to logic".

JJack_0-1658297224844.png

So, for my understanding a safe way for the application processor would be to

  • disable the clock supervision of the PLL output clock (if it was previously enabled)
  • set CLK_PLL_CONFIG.BYPASS_SEL to 2 (PLL_REF), now CM4 runs on input clock of PLL
  • disable the PLL with CLK_PLL_CONFIG.ENABLE = 0
  • reconfigure the divider
  • set CLK_PLL_CONFIG.BYPASS_SEL to 0 (AUTO)
  • re-enable the PLL
  • wait for CLK_PLL_STATUS is LOCKED, maybe implement some timeout supervision here
  • re-activate clock supervision for the new clock frequency

Consider the number of clock cycles the CLK_PLL_CONFIG register description quotes for latency before settings take effect / before subsequent settings should be made (like "When changing BYPASS_SEL, do not turn off the reference clock or PLL clock for five cycles (whichever is slower).")

Good luck

JJACK

Addendum: In the context of a Phased Locked Loop, a control loop, "locked" means that transients have died down, regulation has stabilized an that the actual value at the output is equal to the reference value.

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2 Replies
AS_36
Moderator
Moderator 500 replies posted 250 solutions authored 250 replies posted
Moderator

Hi @Venkatesh 

Could you please elaborate a little more regarding your application? Why exactly do you want to reconfigure the PLL? Also, we didn't understand what you meant by 'PLL settings(CM4) after PLL is locked in CM0+'. Could you please explain what you mean by this CM4 and CM0+ reference?

Regards.

0 Likes
JJack
Level 4
10 likes received 25 replies posted 10 solutions authored
Level 4

Hi Venkatesh,

I guess you mean

Can the application processor (CM4) safely reconfigure the PLL which is in its own clockpath?

The register manual says "do not change settings while the PLL is enabled and connected to logic".

JJack_0-1658297224844.png

So, for my understanding a safe way for the application processor would be to

  • disable the clock supervision of the PLL output clock (if it was previously enabled)
  • set CLK_PLL_CONFIG.BYPASS_SEL to 2 (PLL_REF), now CM4 runs on input clock of PLL
  • disable the PLL with CLK_PLL_CONFIG.ENABLE = 0
  • reconfigure the divider
  • set CLK_PLL_CONFIG.BYPASS_SEL to 0 (AUTO)
  • re-enable the PLL
  • wait for CLK_PLL_STATUS is LOCKED, maybe implement some timeout supervision here
  • re-activate clock supervision for the new clock frequency

Consider the number of clock cycles the CLK_PLL_CONFIG register description quotes for latency before settings take effect / before subsequent settings should be made (like "When changing BYPASS_SEL, do not turn off the reference clock or PLL clock for five cycles (whichever is slower).")

Good luck

JJACK

Addendum: In the context of a Phased Locked Loop, a control loop, "locked" means that transients have died down, regulation has stabilized an that the actual value at the output is equal to the reference value.