【CYT4BF】如何开启PLL 展频功能

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GavinLi
Level 3
Level 3
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Hi 贵司的技术大牛,

想请教一下,如何开启/使用该芯片PLL 的展频功能?有什么详细的步骤或是相关case可以参考吗?

谢谢!

Gavin

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Janine_Y
Moderator
Moderator
Moderator
50 solutions authored 10 likes received 25 solutions authored

Hi Gavin,

关于SSCG功能的setting请参考AN224434

Janine_Y_0-1706683213652.png

底下也有相关代码可以参考。

BR,

Janine

 

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Janine_Y
Moderator
Moderator
Moderator
50 solutions authored 10 likes received 25 solutions authored

Hi Gavin,

关于SSCG功能的setting请参考AN224434

Janine_Y_0-1706683213652.png

底下也有相关代码可以参考。

BR,

Janine

 

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Hi Janine,

感谢你的回复!

顺便问一下,CYT4BF 可以将某个PLL时钟 (经分频后),引至某个pin 上以判断配置是否准确(类似将该pin 设置成clk_out功能,然后通过某个寄存器进行选择将哪个时钟源输出到该clk_out上)?若是有这样的功能,相关怎么配置,是否也有参考工程或是代码?

谢谢!

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Janine_Y
Moderator
Moderator
Moderator
50 solutions authored 10 likes received 25 solutions authored

Hi Gavin.

据我了解,你所说的功能应该是没有,只有一些外设例如SPI 有clk引脚的输出,应该没有单独将某个时钟输出至pin脚上。

BR,

Janine

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