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TRAVEO™ T2G Forum Discussions

lihaiyong
Level 1
Level 1
First question asked Welcome!

1.The CYT4BB bootloader driver was transplanted from Cypress T2G SDL7.6. After the clock frequency division was modified, CM7_0 and CM7_1 core could be started for online debugging, but M7_0 and M7_1 could not be started for self-starting and the CM0 plus core failed to boot.

2.CYT4BF power supply uses LDO mode.

3.The "if(IsConfigured() == false)" branch and "while((IsSequencerBusy() == true) || (IsEnabled() " in the SwitchToExternal function in the cy_power file are commented out, and the CYT4BB three cores can be started successfully.

4.Please tell me the reason for this problem, thanks!

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1 Solution
AS_36
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

Hi @lihaiyong 

If you are using LDO, you will have to change the VCCD source to internal. You can do this by modifying the following file inside SDL - T2G_Sample_Driver_Library_7.6.0\tviibh4m\src\system\rev_b\system_cyt4bb.h.

In system_cyt4bb.h file, in section 'VCCD selection' you should change the -

#define CY_SYS_VCCD_SOURCE CY_SYS_VCCD_PMIC to #define CY_SYS_VCCD_SOURCE CY_SYS_VCCD_INTERNAL

Then, in the same file, you should also change the PLL frequency to 160MHz, because that is the only supported value.

Please perform these steps and let us know if it works for you.

You can also go through this application note - https://www.infineon.com/dgdl/Infineon-AN226698_External_power_supply_design_guide_for_TRAVEO_T2G_fa...

Regards.

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AS_36
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

Hi @lihaiyong 

If you are using LDO, you will have to change the VCCD source to internal. You can do this by modifying the following file inside SDL - T2G_Sample_Driver_Library_7.6.0\tviibh4m\src\system\rev_b\system_cyt4bb.h.

In system_cyt4bb.h file, in section 'VCCD selection' you should change the -

#define CY_SYS_VCCD_SOURCE CY_SYS_VCCD_PMIC to #define CY_SYS_VCCD_SOURCE CY_SYS_VCCD_INTERNAL

Then, in the same file, you should also change the PLL frequency to 160MHz, because that is the only supported value.

Please perform these steps and let us know if it works for you.

You can also go through this application note - https://www.infineon.com/dgdl/Infineon-AN226698_External_power_supply_design_guide_for_TRAVEO_T2G_fa...

Regards.

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