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hungthanh95
Level 1
Level 1
First reply posted First question asked Welcome!

Hi Infineon team,

I'd run chip CYT3BB7CEBQ0AESGST using SDL 7.7.

I boot the CM0 chip using the Boot folder from SDL. 

Configure:

System init clock in file system_tviibh4m_cm0plus.c (sample with ECO=16MHz).

I using external crystal 8MHz (ECO = 8MHz). So I just changed CY_SYSTEM_PLLx_CONFIG_REFDIVCY_SYSTEM_PLLx_CONFIG_FEEDBACKDIVCY_SYSTEM_PLLx_CCONFIG_OUTDIV

to get PLL0 = 250 MHz

#define CY_SYSTEM_PLL0_CONFIG_REFDIV (2UL)
#define CY_SYSTEM_PLL0_CONFIG_FEEDBACKDIV (125UL)
#define CY_SYSTEM_PLL0_CONFIG_OUTDIV (4UL)

PLL1 = 196607999.92Hz

#define CY_SYSTEM_PLL1_CONFIG_REFDIV (1UL)
#define CY_SYSTEM_PLL1_CONFIG_FB_INT (98UL)
#define CY_SYSTEM_PLL1_CONFIG_FB_FRAC (5100273UL)
#define CY_SYSTEM_PLL1_CONFIG_OUTDIV (4UL)

PLL2 = 160MHz

#define CY_SYSTEM_PLL2_CONFIG_REFDIV (1UL)
#define CY_SYSTEM_PLL2_CONFIG_FEEDBACKDIV (40UL)
#define CY_SYSTEM_PLL2_CONFIG_OUTDIV (4UL)

PLL3 = 80MHz

#define CY_SYSTEM_PLL3_CONFIG_REFDIV (2UL)
#define CY_SYSTEM_PLL3_CONFIG_FEEDBACKDIV (80UL)
#define CY_SYSTEM_PLL3_CONFIG_OUTDIV (4UL)

Clock HFx:

    /***  Setting for each clk_hf        ***/
    struct {cy_en_hf_clk_dividers_t targetDiv; cy_en_hf_clk_sources_t source;} clkHfSetting[SRSS_NUM_HFROOT] =
    {
        { .targetDiv = CY_SYSCLK_HFCLK_NO_DIVIDE,   .source = CY_SYSCLK_HFCLK_IN_CLKPATH3 /* PLL2: PLL200#0 */ }, // setting for clk_hf0
        { .targetDiv = CY_SYSCLK_HFCLK_NO_DIVIDE,   .source = CY_SYSCLK_HFCLK_IN_CLKPATH1 /* PLL0: PLL400#0 */ }, // setting for clk_hf1
        { .targetDiv = CY_SYSCLK_HFCLK_NO_DIVIDE,   .source = CY_SYSCLK_HFCLK_IN_CLKPATH4 /* PLL3: PLL200#1 */ }, // setting for clk_hf2
        { .targetDiv = CY_SYSCLK_HFCLK_DIVIDE_BY_2, .source = CY_SYSCLK_HFCLK_IN_CLKPATH3 /* PLL2: PLL200#0 */ }, // setting for clk_hf3
        { .targetDiv = CY_SYSCLK_HFCLK_DIVIDE_BY_4, .source = CY_SYSCLK_HFCLK_IN_CLKPATH2 /* PLL3: PLL400#1 */ }, // setting for clk_hf4
        { .targetDiv = CY_SYSCLK_HFCLK_NO_DIVIDE,   .source = CY_SYSCLK_HFCLK_IN_CLKPATH2 /* PLL1: PLL400#1 */ }, // setting for clk_hf5
        { .targetDiv = CY_SYSCLK_HFCLK_NO_DIVIDE,   .source = CY_SYSCLK_HFCLK_IN_CLKPATH3 /* PLL3: PLL200#1 */ }, // setting for clk_hf6
        { .targetDiv = CY_SYSCLK_HFCLK_NO_DIVIDE,   .source = CY_SYSCLK_HFCLK_IN_CLKPATH5 /* No PLL/FLL */     }, // setting for clk_hf7
    };
 

Issues:

I use SDL API:

Cy_SysClk_GetPllOutputFrequency:
-> PLL400#0: 250MHz
-> PLL400#1: 196.60799992 MHz
-> PLL200#0: 160MHz
-> PLL200#1: 80MHz
Cy_SysClk_GetFast0Frequency:
-> 250MHz
Cy_SysClk_GetClkMemFrequency:
 -> 160MHz
Cy_SysClk_GetClkSlowFrequency
-> 80MHz

 

It seems to be OK. But when I run CM0 will reset and can't jump to CM7_0. 

If I reduce all PLL output clocks by half -> CM0 and CM7_0 run normally (but the clock is 1/2 smaller than desired)

If I use external crystal 16MHz and the default file system_tviibh4m_cm0plus.things ok (CM0 and CM7_0 run normally).

 

Questions:

1. I think refdiv, feedbackdiv, and output are ok following the restrictions of the datasheet (Infineon-TRAVEO_T2G_CYT3BB_4BB-DataSheet-v09_00-EN.pdf).

But why chip can't run as expected?

2. Do I need to edit other values such as ROM/RAM waitstate and FLASH wait cycle?
If yes then what should the value be I can't find the reference.

 

Please help me to resolve these issues (Refer to file system_tviibh4m_cm0plus.c for more detail).

 

Thank you Infineon team.

 

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2 Replies
Imam_M
Moderator
Moderator
Moderator
25 solutions authored 50 replies posted 10 likes received

Hi @hungthanh95,

We checked the datasheet for the device that you mentioned and there are no restrictions you met.

For your question number 2. Do I need to edit other values such as ROM/RAM waitstate and FLASH wait cycle?
If yes then what should the value be I can't find the reference.

For SRAM/SROM wait states, it depends on the number of CLK_MEM. kindly refer to the following information from Architecture TRM.

Imam_M_0-1713197149026.png

Imam_M_1-1713197202634.png

 

 

Before implementing wait states, what we could recommend to you while implementing this configuration, you could place a small delay (around 100 us) before starting CM7 and check if this works. Thank you.

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hungthanh95
Level 1
Level 1
First reply posted First question asked Welcome!

Hi @Imam_M ,

 I configured PLL400#0 with 250MHz.

 

hungthanh95_1-1713243335686.png

Here is my output:

I used this API MeasureClockFrequency (refer to samples sysclk).
Expected: 250MHz
Actual: 233.24MHz

hungthanh95_2-1713243451108.png

And when run which high speed (> 190MHz)
The board will error and can not debugger.

hungthanh95_3-1713243501797.png

Do you have any suggestions about this issue or can you provide me a sample of cyt3bb using ECO 8MHz?

Thank you.

Best regards,

Thanh Le.

 

 

 

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