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TRAVEO™ T2G Forum Discussions

willywillcont
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Hello,

We are testing CYT3BB chip on board level in DeepSleep mode, out of 10 boards we found 1 board with high sleep current issue.

There are a few unused pins and we left floating (NC). We found some NC pins have voltage spikes even during DeepSleep. We also measure current spikes on supply going into MCU VDDD pins every 600us. 

We found these voltage and current spikes correlates with each other.  

Measuring on VDDD, VCCD, and VDDIO, there is ripple voltage from low to high every time when the current spikes.

Question:

- What might cause the MCU to consume temporary current that causes current spikes at short interval?

- How to check if the floating pins are input disabled?

- Where else can I troubleshoot to eliminate leakage path ?

 

Cheers,

William

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abhikul
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Hello @willywillcont 

>>What might cause the MCU to consume temporary current that causes current spikes at short interval?

Make sure while in Deepsleep mode your debugger is disconnected so has to avoid debugger errors as debugger might consume more power.

>>How to check if the floating pins are input disabled?

To answer this question, I have certain questions:

  1. Can you specify which pins you are kept as NC?
  2. Can you also specify any external supply is applied to VCCD pin?

I have the following questions:

  1. Can you specify which evaluation board you are using for CYT3BB device? Is it Infineon evaluation board or your own customized board?
  2. Also, can you please state that, for 10 boards the configuration used is same or different. 

>>Where else can I troubleshoot to eliminate leakage path?

There is one application note which explains about hardware design in Traveo 2. So, in this note refer section " Port and non-power pins " which explains about how handle the unused pins and also eliminate the effect of the unused pins. The link for the same is:

https://new-origin.infineon.com/dgdl/Infineon-Hardware_Design_Guide_for_the_Traveo_II_Family-Applica...

Thanks & Regards

Abhishek Kulkarni

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Hi @abhikul 

>>> Make sure while in Deepsleep mode your debugger is disconnected so has to avoid debugger errors as debugger might consume more power.

The debugger is disconnected at all times.

 

>>> Can you specify which pins you are kept as NC?

P7.0, P7.2, P7.4, P8.2, P11.0, P11.1, P12.4

 

>>> Can you also specify any external supply is applied to VCCD pin?

There is no external supply to VCCD pin.

 

>>> Can you specify which evaluation board you are using for CYT3BB device? Is it Infineon evaluation board or your own customized board?

It is a customized board.

 

>>> Also, can you please state that, for 10 boards the configuration used is same or different. 

Firmware and configurations are identical across 10 boards.

 

I have read AN220270 on the 7.1.1 Open pin connection. A question on the pin configuration, pins listed above are NC pins without long traces (left as floating). What would be the recommendation as pin configuration? That is, Input or Output? DRIVE_MODE = ? as per AN220118.

 

Thanks,

William

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Hello @willywillcont 

Thanks a lot for the inputs.

Can you please change the chip of the board in which the current issue is observed and replace the chip from any working board and check if the same current issue is observed or not.

Also make sure that you have connected all the ADC supply pins (VDDA, VSSA, VREFH, and optionally VREFL), even if the ADC is not used so as to eliminate additional current. I have attached screenshot for the same which is taken from hardware design application note. (Refer image 1).

Also, in hibernate mode the unused pins are configured to the high-impedance drive mode with input buffer disabled so as to achieve the lowest device current.  I have attached screenshot for the same which is taken from technical reference manual of the device. (Refer image 2).

Thanks & Regards

Abhishek Kulkarni

 

 

 

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Hi @abhikul 

Thanks for your prompt response as well.

>>> Can you please change the chip of the board in which the current issue is observed and replace the chip from any working board and check if the same current issue is observed or not.

We tried the above, however the issue seems to follow the board. It is assumed something on board caused the MCU to drain more current than expected during DeepSleep.

 

>>> Also make sure that you have connected all the ADC supply pins (VDDA, VSSA, VREFH, and optionally VREFL), even if the ADC is not used so as to eliminate additional current. I have attached screenshot for the same which is taken from hardware design application note. (Refer image 1).

Currently, VDDA and VREFH is connected to the same 5V power source that supplies VDDD. VSSA and VREFL is connected to the GND that is also connected to VSSD.

 

>>> Also, in hibernate mode the unused pins are configured to the high-impedance drive mode with input buffer disabled so as to achieve the lowest device current.  I have attached screenshot for the same which is taken from technical reference manual of the device. (Refer image 2).

Is it also the same for DeepSleep mode? Just to reconfirm -- unused pins should be configured as Input, but disabled. Correct? 

We found some unused pins were configured as Drive Mode 'Strong', so we changed to 'High-Impedance'. Little improvement - current spike still however occurs.

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Hello @willywillcont 

Thanks a lot for the updates

>>We tried the above, however the issue seems to follow the board. It is assumed something on board caused the MCU to drain more current than expected during DeepSleep.

From this statement it seems that, there might be some fault in your board or in board design compared with boards which are working perfectly.

For the Deepsleep mode too the unused pins should be configured to the high-impedance drive mode with input buffer disabled.

Some questions I have which I need some information:

  1. Can you please check your power rails lines of that board? Is any low impedance path is created between a supply pin and ground?
  2. Also, can you please check does latch-up effect is happening at unused pins? Because sometimes due to board design it may happen.

If latch-up effect is taking place, please refer the section 7.1.3 and 7.1.4 from the hardware design application note so as to terminate the latch-up effect. You can use either of methods stated in the application note.

Thanks & Regards

Abhishek Kulkarni

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willywillcont
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Hi @abhikul 

Thanks for your response and patience, I've just returned from personal leaves.

>>>> Can you please check your power rails lines of that board? Is any low impedance path is created between a supply pin and ground?

Ans: See attached measurement done using LCR Meter, both GOOD and BAD board exhibits identical Impedance measurement @ 1 kHz.

 

>>>> Also, can you please check does latch-up effect is happening at unused pins? Because sometimes due to board design it may happen.

Ans: May I know how to confirm if a latch-up effect occurs? Per AN220270, section 7.5, Latch-up consideration is only when there's a physical switch, which isn't applicable for our application. Or, is there a different understanding?

 

On top of that, I'd like to share about current measurement done after changing pin config from 'STRONG' to 'HIGH-IMPEDANCE', the sleep current measurement improves by more than 50% on the rail (VCC_5V) that supplies to VDDD, VREFH, VDDIO_1, VDDIO_2, VDDA. Reduces from 800~1000uA range to 445 uA, after a prolonged period.

The behaviour is strange though - at first after entering DeepSleep, current consumption reaches around 747uA up to 830uA, but after a while it dropped to 639uA and decreased exponentially to 445uA after 30 minutes. We could not explain why.

 

We are wondering:

As other GOOD boards have NC pins configured as Drive_Mode = STRONG as well, why don't we see high current issue on other GOOD boards, but only on this specific problematic BAD board? As what you suspect there may be some fault in this specific problematic BAD board.  

 

We highly appreciate your expertise and thank you in advance once again. We are still diligently investigating this issue.

 

Thanks and regards,

William

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abhikul
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Hello @willywillcont 

Thanks a lot for your updates!

 

>> May I know how to confirm if a latch-up effect occurs? Per AN220270, section 7.5, Latch-up consideration is only when there's a physical switch, which isn't applicable for our application. Or, is there a different understanding?

Sometimes latch-up effects take place at unused pin due to board design. (Long traces of optional
features). Please refer section 7.1.3 from the same application note for more information about the prevention of this effect.

Thanks & Regards

Abhishek Kulkarni 

 

 

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