CYT2BX Clock_Configuration

[chme_4646286]

请教一个问题：基于CYTVII-B-E-1M-SK 验证clock 相关配置，参考SDL示例工程

T2G_Sample_Driver_Library_7.3.0\tviibe1m\src\examples\sysclk\DifferentCPUClock中main_cm0plus.c；

其中SystemInit()函数中是配置使能了ECO作为PLL的输入源；

且clk_hf0和clk_hf1都选择的是PLL作为源信号；

CYTVII-B-E-1M-SK 上16M的外部晶振并没有贴片，但启动debug后，cm0内核还是可以正常运行；

疑问：此处时钟配置使能ECO作为HF0/HF1的时钟源，但是ECO不存在，那后续的HF clock是如何产生的呢？

TRM手册有无对应的说明？

期待您的解答，谢谢~~

[Alfred_Tsang · Accepted solution]

Hello Chme,

This is because there is no ECO mounted on CYTVII-B-E-1M-SK, and the kit board is using IMO for the clock source.

In order to run the kit board "STARTER_KIT_REV3" and "CY_MCU_rev_d" macro has been defined during if you selected "starter_kit" for the configuration setup. 

Then macro "CY_SYSTEM_USE_IMO" is defined for the clock source in system_cyt2b7.h (T2G_Sample_Driver_Library_7.3.0\tviibe1m\src\system\rev_d)

Best regards

[chme_4646286]

Hi shingT_76，

非常感谢，我也找到了此处的宏定义；

关于IMO和ECO时钟源，引申出另一个问题：

参考datasheet，T2G的SCB_UART其波特率最大可用支持到10M；

那如果我需要设置uart的波特率为10M，此时我选择的时钟源可用是IMO吗？

因为我使用startkit调试的时候，当uart波特率设置2M的时，debug状态下数据接收异常，但是不启动debug模式，数据发送就是正常的，所有我怀疑debug调试模式下，是否不支持高速率；

[Alfred_Tsang]

Hi Chme,

For the UART baud rate, in DS, it is 10MHz. But it is only the MCU specification, which does not consider other factors.

Refer to UART module datasheet, the calculation of UART clock tolerance is 3.9% for 8 oversampling and 4.6% for 16 oversampling. It means that the clock difference between the two devices can fulfill those values, then it is possible to receive UART data without error. For more information, please refer to attached document.

I am assume that customer are using USB-UART on KitProg3, for the KitProg3 operating speeds, USB-UART bridge is up to 4MHz (for Data bits -8, Parity- None, Stop bits -1). But, it does not mention that it can be used at the same time with the debugger for the max. supported speed.

Best regards,

[chme_4646286]

Hi shingT_76，

感谢你的答复，我自己在研究下这里面的差异；