[CYT2B98] About Event generator period with & without JTAG Debugger

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WonjinHan
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Dears.

 

Now I use event generator in CYT2B98CAS with evaluation board of CYTVII-B-E-176-SO.

Event generator operation is working well. Whenever event generator triggers interrupt like 20ms, it enables output gpio pulse. (No problem)

However, strange thing is that if I hook up the T32 debugger to this EVB and evoke software FW like run time debugging,

Interval interrupt time of event generator is more extended like it triggers event generator interrupt every 50ms.

 

Could you tell me why it happened inside of it?

 

Software environment is as the following.

Used SDL version : SDL 7.9.0

Reference Code : T2G_Sample_Driver_Library_7.9.0\tviibe2m\src\examples\evtgen\dpslp_wakeup

Main clock : IMO

DeepSleep Event Generator Interval : 20ms

 
Test Code is as the following.
 
//--------------------------------------------------------------------------------------------------------
void irqEVTGEN_sleep(void)
{
    /*
      waiting until counter become ready before set new compare value.
      This waiting may take up to 1 clk_lf cycle from wakeup.
    */
    while(Cy_Evtgen_GetCounterStatus(EVTGEN0) == CY_EVTGEN_COUNTER_STATUS_INVALID);

    Cy_Evtgen_ClearStructInterruptDeepSleep(EVTGEN0,0);
}
 
//--------------------------------------------------------------------------------------------------------
In main function 
 
 
    /*******************************************/
    /*        Deinitialize peripherals         */
    /*******************************************/
    Cy_Evtgen_DeinitializeCompStruct(EVTGEN0,0);
    Cy_Evtgen_Deinitialize(EVTGEN0);
    NVIC_ClearPendingIRQ(CPUIntIdx3_IRQn);

    /*******************************************/
    /*  Interrupt setting for Event Generator  */
    /*******************************************/
    irq_cfg.sysIntSrc  = evtgen_0_interrupt_dpslp_IRQn;
    irq_cfg.intIdx     = CPUIntIdx3_IRQn;
    irq_cfg.isEnabled  = true;
    Cy_SysInt_InitIRQ(&irq_cfg);
      Cy_SysInt_SetSystemIrqVector(evtgen_0_interrupt_dpslp_IRQn, irqEVTGEN_sleep);
    NVIC_ClearPendingIRQ(CPUIntIdx3_IRQn);
    NVIC_EnableIRQ(CPUIntIdx3_IRQn);

    CyclicWakeup_EventGenerator_Init();
    /* Set next event generator wakeup time */
      evtgenStructureConfig.valueDeepSleepComparator = CYCLIC_WAKEUP_PERIOD;
    /* Put the system to DeepSleep */
    while(1)
    {
        // Deepsleep : 100ms
        Cy_GPIO_Write(USER_PORT, USER_PIN, 0);
        /* Update current counter value for next event */
        currentCounterValue = (uint64_t)Cy_Evtgen_GetCounterValue(EVTGEN0);
        /* calculate next compare value of event generator */
        saveCountValue = (uint32_t)(currentCounterValue + (uint64_t)evtgenStructureConfig.valueDeepSleepComparator);
        /* set next compare value of event generator */
        Cy_Evtgen_SetValueComp(EVTGEN0, 0,saveCountValue);

        Cy_SysPm_DeepSleep((cy_en_syspm_waitfor_t)CY_SYSPM_WAIT_FOR_INTERRUPT);

        // Active : 10ms
        Cy_GPIO_Write(USER_PORT, USER_PIN, 1);
        Cy_SysTick_DelayInUs(10000);
    }
}
void CyclicWakeup_EventGenerator_Init(void)
{
    Cy_Evtgen_DeinitializeCompStruct(EVTGEN0,0);
    Cy_Evtgen_Deinitialize(EVTGEN0);

    /*******************************************/
    /*  Initialize event generator  0          */
    /*******************************************/
    evtgenConfig.frequencyRef = 8000000; //  clk_ref = clk_hf1 = CLK_PATH2 (IMO) -> 8,000,000 for silicon
    evtgenConfig.frequencyLf = 32768; //32000;     // clk_lf = 32,000 for silicon

    evtgenConfig.frequencyTick = 1000000; // Setting 1,000,000 Hz for event generator clock (clk_ref_div)
    evtgenConfig.ratioControlMode = CY_EVTGEN_RATIO_CONTROL_SW;
    evtgenConfig.ratioValueDynamicMode = CY_EVTGEN_RATIO_DYNAMIC_MODE0;
    Cy_Evtgen_Initialize(EVTGEN0,&evtgenConfig);

    /*******************************************/
    /*  Initialize comparator structure 0      */
    /*******************************************/
    evtgenStructureConfig.functionalitySelection = CY_EVTGEN_DEEPSLEEP_FUNCTIONALITY;
    evtgenStructureConfig.triggerOutEdge = CY_EVTGEN_EDGE_SENSITIVE;

    evtgenStructureConfig.valueDeepSleepComparator = 20000;//100000;
// In active functionality, this value is used for making period of interrupts/triggers
// 100,000 / 1,000,000 (clk_ref_div) = 0.1[s]
 
    evtgenStructureConfig.valueActiveComparator    = 0;
// In active functionality, this value is used for making period of interrupts/triggers
// 1,000,000 / 1,000,000 (clk_ref_div) = 1[s]
 
    Cy_Evtgen_InitializeCompStruct(EVTGEN0,0, &evtgenStructureConfig, &evtgenStruct0Context);
}
 
  //--------------------------------------------------------------------------------------------------------
 

Best regards,

Kevin Han.

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1 Solution
Reza_A
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100 replies posted 25 solutions authored 10 likes given

Hi @WonjinHan,

Apologies for the delayed response,

I checked your code, the configurations for EVTGEN and it's interrupt is already proper.

The DeepSleep counter functionality is available in both the Active and DeepSleep power modes, however, there is a difference regarding how the DeepSleep counter is incremented between both power modes. This difference between Active and DeepSleep counter is as described in the Architecture TRM, sub-section 28.2.4 DeepSleep Counter update.

In Active power mode, the active counter is functional, and the counter will be incremented every clk_ref_div cycle. In every clk_lf cycle, the deepsleep counter copies value as the active counter, ensuring the counters to be in sync.

However, in the DeepSleep power mode, the active counter is not incrementing, and the DeepSleep power mode will be incremented based on the "RATIO" register value. In your code, you are configuring the RATIO value by SW (CY_EVTGEN_RATIO_CONTROL_SW). By the SDL, RATIO will be calculated in the Cy_Evtgen_Initialize, as (frequencyRef/(frequencyRef/ frequencyTick)/ frequencyLf), where the values are user-defined.

The difference of interrupt interval in Active mode and DeepSleep mode might be caused by the difference of the calculated RATIO, and the true ratio (clk_div_rev/ clk_lf). While in active mode, the DeepSleep counter will be incremented with the true ratio (because it's copies the active counter), while in DeepSleep mode, the DeepSleep counter will be incremented by the calculated RATIO. Please check the following:

1. Please try setting the ratioControlMode to CY_EVTGEN_RATIO_CONTROL_HW. This will re-calibrate the RATIO value by measuring the ratio. More details could be found in the EVTGEN0_RATIO_CTL description in the Register TRM.

2. Please check your clock pre-divider configurations (CLK_ROOT_SELECT[x].ROOT_DIV) and see if the clock is actually pre-divided. If so, kindly configure the clock pre-divider or change the frequencyRef.

When you are debugging your firmware, attempting to enter DeepSleep mode will go to Sleep power mode instead, as described in the Architecture TRM also. The behavior of the EVTGEN in sleep power mode is the same as it is in active mode, this is why the issue is observed when you are debugging, as well as when you replace Cy_SysPm_DeepSleep to Cy_SysPm_Sleep.

I hope this helps.

Best regards.

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WonjinHan
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Hello. 

I tried to do the following modification code without JTAG debugger, the result is the same as in condition like event generator period extends from 20ms to almost 50ms. 

        //Cy_SysPm_DeepSleep((cy_en_syspm_waitfor_t)CY_SYSPM_WAIT_FOR_INTERRUPT);
        Cy_SysPm_Sleep((cy_en_syspm_waitfor_t)CY_SYSPM_WAIT_FOR_INTERRUPT);
 
Please give me your opinion. 
 
Best regards, 
Kevin Han. 
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Reza_A
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100 replies posted 25 solutions authored 10 likes given

Hi @WonjinHan,

We will test this at our end also and we will update this thread as soon as possible.
Thank you.

Best regards.

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WonjinHan
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Hello Reza_A.
Thank you for your answer.

If you have any update, I would like you to keep us posted.

Best regards,
Kevin Han.

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Reza_A
Moderator
Moderator
Moderator
100 replies posted 25 solutions authored 10 likes given

Hi @WonjinHan,

Apologies for the delayed response,

I checked your code, the configurations for EVTGEN and it's interrupt is already proper.

The DeepSleep counter functionality is available in both the Active and DeepSleep power modes, however, there is a difference regarding how the DeepSleep counter is incremented between both power modes. This difference between Active and DeepSleep counter is as described in the Architecture TRM, sub-section 28.2.4 DeepSleep Counter update.

In Active power mode, the active counter is functional, and the counter will be incremented every clk_ref_div cycle. In every clk_lf cycle, the deepsleep counter copies value as the active counter, ensuring the counters to be in sync.

However, in the DeepSleep power mode, the active counter is not incrementing, and the DeepSleep power mode will be incremented based on the "RATIO" register value. In your code, you are configuring the RATIO value by SW (CY_EVTGEN_RATIO_CONTROL_SW). By the SDL, RATIO will be calculated in the Cy_Evtgen_Initialize, as (frequencyRef/(frequencyRef/ frequencyTick)/ frequencyLf), where the values are user-defined.

The difference of interrupt interval in Active mode and DeepSleep mode might be caused by the difference of the calculated RATIO, and the true ratio (clk_div_rev/ clk_lf). While in active mode, the DeepSleep counter will be incremented with the true ratio (because it's copies the active counter), while in DeepSleep mode, the DeepSleep counter will be incremented by the calculated RATIO. Please check the following:

1. Please try setting the ratioControlMode to CY_EVTGEN_RATIO_CONTROL_HW. This will re-calibrate the RATIO value by measuring the ratio. More details could be found in the EVTGEN0_RATIO_CTL description in the Register TRM.

2. Please check your clock pre-divider configurations (CLK_ROOT_SELECT[x].ROOT_DIV) and see if the clock is actually pre-divided. If so, kindly configure the clock pre-divider or change the frequencyRef.

When you are debugging your firmware, attempting to enter DeepSleep mode will go to Sleep power mode instead, as described in the Architecture TRM also. The behavior of the EVTGEN in sleep power mode is the same as it is in active mode, this is why the issue is observed when you are debugging, as well as when you replace Cy_SysPm_DeepSleep to Cy_SysPm_Sleep.

I hope this helps.

Best regards.

WonjinHan
Level 4
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Distributor
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Hello Reza_A.


I really appreciate your feedback.

Thanks to your description, I could make it correct as the following

<1>
/* Select source of clk_hf1 */
/*** Set HF1 source, divider, enable ***/
SRSS->unCLK_ROOT_SELECT[1/*clk_hf1*/].stcField.u4ROOT_MUX = CY_SYSCLK_HFCLK_IN_CLKPATH1;
SRSS->unCLK_ROOT_SELECT[1].stcField.u2ROOT_DIV = 0u; /* divided by 1 */
SRSS->unCLK_ROOT_SELECT[1].stcField.u1ENABLE = 1u; /* 1 = enable */

<2>
In LPWakeup , I used IMO to make the PLL enabled in 160Mhz. 

In Result, Operation is working well.

Thanks and Best regards,
Kevin Han.

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