TRAVEO™ T2G Forum Discussions

[tigercat]

Hello,

I'm looking for documentation for SFlash. I would like to know what it is, how to use it.

I searched on the official site (https://www.infineon.com/cms/en/product/microcontroller/32-bit-traveo-t2g-arm-cortex-microcontroller...) but could not find the detail.

Looking forward to some help. 🙂

[AS_36]

Hi @tigercat 

You can find more information on SFlash in the architecture TRM of the device. You can get access to the TRM and many other Traveo T2G related documentation by joining MyICP which is our collaboration platform for file sharing.

You can join MyICP by following the steps mentioned on this link - https://www.infineon.com/cms/en/product/microcontroller/#!details

You can also read the following application note on flash accessing procedure - https://www.infineon.com/dgdl/Infineon-Flash_Rewriting_Procedure_for_Traveo_II_Family-ApplicationNot...

You can also refer to this FAQs document on flash - https://community.infineon.com/t5/Knowledge-Base-Articles/Traveo-II-Automotive-Body-Controller-FAQ-F...

Regards.

[tigercat]

THanks you very much for reply.

1. I joined MyICP.  Could you please tell me the keyword so that I can search it? 

2. I checked flash accessing procedure document and FAQ. However, I cannot find information that I'm looking for. (what supervisory flash is, structure, detail memory map, how to use it , sample codes)

Thank you very much again for your help. 🙂

[AS_36]

Hi @tigercat 

Please refer the TRAVEO™ T2G Architecture TRM for Body Entry devices (002-19314) (Traveo II -> Traveo II Body -> Technical Reference Manual (TRM)). You can find details (what supervisory flash is, structure, detail memory map) about supervisory area in chapters 8 and 9. Flash operations are implemented as system calls and you can refer to chapter 33 to learn more about it.

Hope this answers your question.

Regards.

[tigercat]

I do appreciate for the name of document and the chapter number. It helped me a lot. However, I still have questions that cannot be solved by the TRM document.

1. Is "Supervisory" flash memory(Sflash) physically seperated from Code/Work flash? or
    Is it the part of code/work flash memory? what is the physical  memory features like one-time-programmable??

2. In datasheet address map, I can see two 32K Sflash area(0x1700 0000~7FFF, 0x1780 0000~7FFFF).
    Do these two Sflash(64K) actually exists?  Datasheet says cyt2b9 has 2M code flash, 128K work flash. 
    I'm wondering if cyt2b9 has additional 64K flash memory.

3. According to TRM, Sflash is used to store some parameters or cypress proprietary. Is there any documents that describes Sflash address map /contents? I expect that some information has fixed Sflash memory address and other area is configurable. I need to know exactly what kind of information can be stored and how to do it and what should I be careful of in terms of the Sflah use.

4. Is there any application note that can answer above my questions?

Thanks again!

[AS_36]

Hi @tigercat 

(1) and (2) In Architecture TRM, the sub section '8.2.3.1 Interface, Regions, and Type of Use' gives some details. SFlash is an additional memory region, excluded from code flash specified in the datasheet. User will be able to modify only certain sections of SFlash (for example user area, public key etc.) .

(3) and (4) Please kindly refer to the TRM. Any further information is confidential and cannot be shared.

Regards.

[tigercat]

I do appreciate for the answers. 

I asked the questions after studied the section 8.2.3.1. 

It says "The top sectors in code flash are assigned as supervisory region and other sectors are assigned as code region".

I am still confused if SFlash is physically seperated from Code flash or the part of code flash is used as SFlash. the reason why I have questions on this is to understand memory map and size.

if SFlash is the part of Code flash, then should I think that 64K code flash memory cannot be used?

or there is addional 64K memory beside 2M code flash?

Thank you very much. 🙂