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Dears
I’m looking for how to make jtag port disable like temporary jtag disable and permanent jtag disable for CYT2B63CAS.
Could you tell me what kinds of methods it has ?
Best regards,
Kevin Han.
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TRAVEO™ T2G
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Hello Kevin,
JTAG locking(temporary/permanent) are configured by the boot code depending upon the user configuration made in dedicated SFlash Rows or efuse bits.
It can be done when we are either in life cycle state NORMAL or SECURE.
In the NORMAL protection state, debug access restrictions are applied by the boot as per the configuration in SFlash address 0x1700 1A00(NAR). This SFlash Row can be written using the ‘WriteRow’ system call.
In the SECURE protection state, we can configure EFUSE bits to enable authenticated debug access, to write into EFUSE bits we need to use Transition to Secure system call.
Both SFLASH/EFUSE bits are having similar structure, details of each bit can be found in "Table 33-87. Access Restrictions Encoding" and "Table 11-6. eFuse Bits Used by BootROM" of TRAVEO_T2G_Automotive_Body_Controller_Entry_Family_Architecture_TRM.
In Normal/Secure protection state, boot will configure CPUSS_AP_CTL register bits based on SFlash/efuse configuration. At any point of time, debug access restrictions are applied/decided by CPUSS_AP_CTL register bits as explained in below table:
CPUSS_AP_CTL.xx_ENABLE | CPUSS_AP_CTL.xx_DISABLE | Debug Access |
1 | 0 | Enabled |
0 | 0 | Authenticated debug access (temporary disabled) |
0 | 1 | Disabled (Permanent disabled, irreversible) |
Please refer section 12.3 of "TRAVEO II AUTOMOTIVE BODY CONTROLLER - FAQ - KBA229757" document and section 16.1.1 of "Secure system configuration in TRAVEO™ T2G family" Application Note(AN228680).
Link for KBA : https://community.infineon.com/t5/Knowledge-Base-Articles/Traveo-II-Automotive-Body-Controller-FAQ-K...
Link for App Note : https://www.infineon.com/dgdl/Infineon-AN228680_Secure_System_Configuration_in_TRAVEO_T2G_Family-App...
Hoping above explanation solves your question.
Thank you.
Regards
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Hello Kevin,
JTAG locking(temporary/permanent) are configured by the boot code depending upon the user configuration made in dedicated SFlash Rows or efuse bits.
It can be done when we are either in life cycle state NORMAL or SECURE.
In the NORMAL protection state, debug access restrictions are applied by the boot as per the configuration in SFlash address 0x1700 1A00(NAR). This SFlash Row can be written using the ‘WriteRow’ system call.
In the SECURE protection state, we can configure EFUSE bits to enable authenticated debug access, to write into EFUSE bits we need to use Transition to Secure system call.
Both SFLASH/EFUSE bits are having similar structure, details of each bit can be found in "Table 33-87. Access Restrictions Encoding" and "Table 11-6. eFuse Bits Used by BootROM" of TRAVEO_T2G_Automotive_Body_Controller_Entry_Family_Architecture_TRM.
In Normal/Secure protection state, boot will configure CPUSS_AP_CTL register bits based on SFlash/efuse configuration. At any point of time, debug access restrictions are applied/decided by CPUSS_AP_CTL register bits as explained in below table:
CPUSS_AP_CTL.xx_ENABLE | CPUSS_AP_CTL.xx_DISABLE | Debug Access |
1 | 0 | Enabled |
0 | 0 | Authenticated debug access (temporary disabled) |
0 | 1 | Disabled (Permanent disabled, irreversible) |
Please refer section 12.3 of "TRAVEO II AUTOMOTIVE BODY CONTROLLER - FAQ - KBA229757" document and section 16.1.1 of "Secure system configuration in TRAVEO™ T2G family" Application Note(AN228680).
Link for KBA : https://community.infineon.com/t5/Knowledge-Base-Articles/Traveo-II-Automotive-Body-Controller-FAQ-K...
Link for App Note : https://www.infineon.com/dgdl/Infineon-AN228680_Secure_System_Configuration_in_TRAVEO_T2G_Family-App...
Hoping above explanation solves your question.
Thank you.
Regards
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Hello KumarAP.
I appreciate your kindly support and it is very helpful for us.
Thanks and best regards,
Kevin Han.