Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
WonjinHan
Level 4
Level 4
Distributor
50 questions asked 100 sign-ins 50 replies posted

Dears. 

The following waveform represents VDDD and XRES. During the process of identifying the cause of the MCU reset, the following waveform was observed. The BOD (Brown-Out Detection) threshold for VDDD is set to 2.7V.

Although VDDD is approaching a value below 2.7V, it quickly drops to 2.5V and then returns to the normal voltage. In this case, it seems that a BOD reset will not occur. We can refer to this as an acceptable VDDD droop (chattering) spec. Is there a specification for acceptable VDDD droop, and if so, could you provide a detailed explanation?

WoHa_955446_0-1688361966540.png

 

Additionally, when the BOD threshold is set to 2.7V, what is the maximum pulse width required for VDDD voltage to remain below 2.7V without triggering a BOD reset? ( It means minimum pulse width for triggering internal Brown-out Detection signal)

Best regards, 

Kevin Han. 

 

0 Likes
1 Solution
Shubham_D
Moderator
Moderator
Moderator
50 solutions authored 100 replies posted 100 sign-ins

Hi @WonjinHan ,

I apologies for the delayed reply. Refer to the figures and SID parameters from the datasheet, as I specified in my earlier comment, for your question.

Q.How long at least VDDD Trip voltage(VTR_2P7_F) should keep up
 in order for that Internal BOD Block clearly recognizes VDDD level got to BOD detection trip point (2.7V) ?

>>for your consideration. I'm explaining on the figure using SID parameters. For clarification, please refer to the image below, where you can see the parameters tDLY_ACT_LVD and tDLY_DS_LVD that are indicated in the figure for transitioning time .

SDESA_0-1691991720936.png

 

 

 

SDESA_1-1691991720950.png

 

  

Refer to the other figures as well, and contact us if you have any other questions.


Thanks ,
Shubham

View solution in original post

0 Likes
5 Replies
Shubham_D
Moderator
Moderator
Moderator
50 solutions authored 100 replies posted 100 sign-ins

Hi @WonjinHan ,

Are you using a customised board or the Infineon-provided CYT2B9 EVK Board? Could you test the code available in the SDL for the BOD test if you're using the EVK board that Infineon provided for quick tests? And do let us know if you notice the same behaviour.

SDL link: https://softwaretools.infineon.com/tools/com.ifx.tb.tool.traveoiisampledriverlibrary
Code Path : T2G_Sample_Driver_Library_7.X.X\tviibe2m\src\examples\syspm

Thanks,
Shubham


0 Likes
WonjinHan
Level 4
Level 4
Distributor
50 questions asked 100 sign-ins 50 replies posted

Hello Shubham

Thank you for your response. 

Yes. it's custom board. I already did it and fully understood the operation scheme of BOD. 

I mean that I need  official electrical hardware feature specification about BOD released from Infineon. 

Even though already read the datasheet and technical reference doc but couldn't find it about following two things. 

1. VDDD minimum pulse width range for triggering internal brown-out detection signal

2. VDDD  maximum pulse width range for non-triggering internal brown-out detection signal

 
 
For your better understanding of my question,  it's easy to see the following my explanation. 
 
WoHa_955446_0-1688431721238.png

 

 

I understood that the recognition process of BOD as the following.

1. VDDD ramps down to VTR_2P7_F ( ex. 2.7V)
2. Internal BOD Block recognizes BOD detection trip point (2.7V)
3. Assert Internal HV BOD Signal

 

My question is

How long at least VDDD Trip voltage(VTR_2P7_F) should keep up in order for that Internal BOD Block clearly recognizes VDDD level got to BOD detection trip point (2.7V) ?

 
 
I would like you to review my upper questions and give me your recommendation again if it's possible. 
 
Thanks and regards, 
Kevin Han. 
 

 

 

 

 

 

 

0 Likes
Shubham_D
Moderator
Moderator
Moderator
50 solutions authored 100 replies posted 100 sign-ins

Hi @WonjinHan ,

Can you please refer the figures ( 26-16, 26-17, 26-20) available in the device specific datasheet(CYT2G-2M (002-22825 Rev. *I)) and respective SIDs ?

Thanks,
Shubham 

0 Likes
WonjinHan
Level 4
Level 4
Distributor
50 questions asked 100 sign-ins 50 replies posted

Hello Shubham. 

It's not clear for me to understand your recommended figures.

Could you give me your  technical easy explanation about " How long at least VDDD Trip voltage(VTR_2P7_F) should keep up in order for that Internal BOD Block clearly recognizes VDDD level got to BOD detection trip point (2.7V) ?" based on your description like  figures ( 26-16, 26-17, 26-20) in datasheet ? 

 

Thanks and regards, 

Kevin Han.

0 Likes
Shubham_D
Moderator
Moderator
Moderator
50 solutions authored 100 replies posted 100 sign-ins

Hi @WonjinHan ,

I apologies for the delayed reply. Refer to the figures and SID parameters from the datasheet, as I specified in my earlier comment, for your question.

Q.How long at least VDDD Trip voltage(VTR_2P7_F) should keep up
 in order for that Internal BOD Block clearly recognizes VDDD level got to BOD detection trip point (2.7V) ?

>>for your consideration. I'm explaining on the figure using SID parameters. For clarification, please refer to the image below, where you can see the parameters tDLY_ACT_LVD and tDLY_DS_LVD that are indicated in the figure for transitioning time .

SDESA_0-1691991720936.png

 

 

 

SDESA_1-1691991720950.png

 

  

Refer to the other figures as well, and contact us if you have any other questions.


Thanks ,
Shubham

0 Likes