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TRAVEO™ T2G

WoHa_955446
Level 4
50 questions asked 100 sign-ins 50 replies posted
Level 4

Dears.

I understood that each one port consists of 8 IO pins and each IO Pin is mapped with GPIO_PRT_CFG_IN.VTRIP_SEL to configures the GPIO pin input buffer voltage threshold mode. For example, PORT 0 consists of 8 IO PINs and in order to configure that input buffer of Port 0_Pin 7 is compatible with TTL, I should set 0x01 in GPIO_PRT_CFG_IN.VTRIP_SEL7_0. Correct ?

If it’s correct, I couldn’t find the VTRIP_SEL7_0 in GPIO_PRT_CFG_IN, only i can see the lower 4bits are available.  Could you give me your opinion ?

Additionally, would you tell me what "S40S", "S40E" and "S40" mean?

 CFG_IN.jpg

 

Best regards,

Kevin Han.

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Swathi
Moderator
Moderator 25 replies posted 25 sign-ins 10 solutions authored
Moderator

Hello Kevin,

These pins are available on 176-LQFP and 144-LQFP pin packages (attachment) and GPIO_PRT7_CFG_IN can be configured. 

Please let us know which pin package you are using. You can find that information under 'Part Number Nomenclature' section of the device datasheet.

And "S40S", "S40E" and "S40" are different technologies, it is unimportant to the user. These terms are used for internal purpose only.

 

Best regards,

Swathi

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