AXI DMA | Returning/Triggering Destination Bus Error

[Incognito_Guy]

Hi

I am trying to do some AXI DMA operation to transfer the data between two locations.

The code that does the AXI DMA Configuration and triggers the operation resides in CM7_0.

After triggering the transfer, I am getting the DESTINATION BUS ERROR.

What does this mean? Also how do we debug this issues?

How is this AXI DMA different from normal DMA. Is it only the speed?

DMA Config:

• Both Source\Destination address are in SRAM.
• 1D Array transfer.

Thanks In Advance!

[Apurva_S]

Hi @Incognito_Guy 

Could you please tell me more about your application and test setup?

Which Traveo T2G device are you using? Are you using our SDL? If yes, which version?

Regards.

[Incognito_Guy]

Hi

Due to some reasons I can't reveal the device/SDL info.

Can you help me out with the causes of those error (i.e. destination bus
error)?

[Incognito_Guy]

@Apurva_S 

The code is working after calling Scb_Disable_Dcache() API. I would like to know the significance of this API. 

Do you know how this works and why is it needed? 

Also please let me know if there is any documentation on this...

[Apurva_S · Accepted solution]

Hi @Incognito_Guy 

Please go through section 6.4.2 of the following application note https://www.infineon.com/dgdl/Infineon-AN224432_Multi_Core_Handling_Guide_in_Traveo_II-ApplicationNo...

Regards.