ARM_M7(CYT4BFX) is slower than ARM_M4 (CYT2B9X)

[bankireddypali]

Hello,

We are experiencing a high CPU load (95%)in the  System which is based on the “CYT4BFBCJE” (ARM_M7)microcontroller running at 160Mhz whereas the other system which is based on CYT2B9X(ARM_M4) has very less CPU load of 25% even though running at half clock speed of 80Mhz .

We are using same vector BSW ,BSW configuration and application software ,but M7 system is running slower than M4.We are using same compiler options in both systems. Not sure why ARM_M7 system is slower than ARM_M4 system.

Could you please help us possible ways to reduce CPU load in M7 system?.

What are steps to enable instruction cache?.

I just added a line SCB_EnableICache();  that reduced CPU Load by 57%.I did not chosen what part of flash memory can be catchable nor enabled MPU, could you please confirm is it okay to enable just instruction cache  alone with out enabling MPU?.

What are the steps to configure Data Cache?.

I followed following steps ,but after enabling MPU ,its going to exception for some reason. Could you please  confirm am I missing some thing here?.

1.ARM_MPU_SetRegionEx(0UL, 0x28050000,ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_16KB));

2.ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);

3.SCB_EnableDCache();

Regards,

Bhaskar

[bankireddypali]

@KumarAP Could you please help me with this thread?. Many thanks.

[Ashish · Accepted solution]

Hi,

To enable DCache- you just use SCB_EnableDCache(); The api [SCB_EnableICache and SCB_EnableDCache] will be applicable to full memory range (it sets up the IC and DC bits respectively in CCR register) , and if MPU is not enabled , the default attribute will apply (Normal, WT for Flash region, Normal, WBWA for SRAM region). However, if MPU is enabled for a region, then it's attribute is applicable to that region (so you can make a region non-cacheable with MPU even if globally the cache setting is enabled). 

Can you use DSB followed by and ISB after applying new MPU configurations?

If the fault is still trigger- can you check at which line it triggers? And what's the value of FSRs (HFSR,MMSFR,UFSR,BFSR) ? And please share screenshot of call-stack. Also, the XN is set to 1, so if it's trying to execute from this region- it'll trigger fault- you may test it by setting to 0. 

Regards,

Ashish

[bankireddypali]

Hi Ashish,

Thanks for your reply. I am able to choose the Flash memory region and enable MPU  that works okay but if I choose the RAM region in MPU and enable data cache then it results in an exception.

Please find attached details.

I am configuring MPU regions as below. Could you please correct me if I am doing anything wrong for the Data cache?I

ARM_MPU_SetRegionEx(0UL, 0x10000000UL, ARM_MPU_RASR(/*DisableExec*/0UL, /*AccessPermission*/ARM_MPU_AP_FULL,/*TypeExtField*/ 0UL, /*IsShareable*/0UL, /*IsCacheable*/0UL, /*IsBufferable*/0UL, /*SubRegionDisable*/0x00UL, /*Size*/ARM_MPU_REGION_SIZE_4MB));

ARM_MPU_SetRegionEx(1UL, 0x10460000UL, ARM_MPU_RASR(/*DisableExec*/0UL, /*AccessPermission*/ARM_MPU_AP_FULL,/*TypeExtField*/ 0UL, /*IsShareable*/0UL, /*IsCacheable*/0UL, /*IsBufferable*/0UL, /*SubRegionDisable*/0x00UL, /*Size*/ARM_MPU_REGION_SIZE_1KB));

ARM_MPU_SetRegionEx(2UL, 0x10460520UL, ARM_MPU_RASR(/*DisableExec*/0UL, /*AccessPermission*/ARM_MPU_AP_FULL,/*TypeExtField*/ 0UL, /*IsShareable*/0UL, /*IsCacheable*/1UL, /*IsBufferable*/0UL, /*SubRegionDisable*/0x00UL, /*Size*/ARM_MPU_REGION_SIZE_2MB));

ARM_MPU_SetRegionEx(3UL, 0x10660800UL, ARM_MPU_RASR(/*DisableExec*/0UL, /*AccessPermission*/ARM_MPU_AP_FULL,/*TypeExtField*/ 0UL, /*IsShareable*/0UL, /*IsCacheable*/0UL, /*IsBufferable*/0UL, /*SubRegionDisable*/0x00UL, /*Size*/ARM_MPU_REGION_SIZE_1MB));

ARM_MPU_SetRegionEx(4UL,0x28058000UL, ARM_MPU_RASR(/*DisableExec*/0UL, /*AccessPermission*/ARM_MPU_AP_FULL,/*TypeExtField*/ 0UL, /*IsShareable*/0UL, /*IsCacheable*/1UL, /*IsBufferable*/1UL, /*SubRegionDisable*/0x00UL, /*Size*/ARM_MPU_REGION_SIZE_128KB));

Regards,

Bhaskar

[Ashish]

Hi Bhaskar,

Is the stack pointer in cached-memory area? Can you make it (stack region) non-cacheable and check? (If there is any cache-maintenance operation,  it may affect it ). 

Thanks,

Ashish

[Ashish]

Hi Bhaskar,

Any update in this? 

Regards,

Ashish 

[bankireddypali]

Hi Ashish,

Thank you for your feedback.

sorry for the late reply,If I exclude  certain RAM memory range, I am able to setup the data cache working and I can see CPU load is reduced by  20% and after enabling the instruction cache,I can see CPU load reduced from 95% to 38%  and with both Data and instruction cache enabled ,overall load is just 18% (reduced from 95%)

But I have other issues at the moment , code gets struck indefinitely for a handshake between m4 and m7 for security unlocking even though I choose these parts of the software as non-catchable, working internally on this issue at the moment.

There is also a recommendation to move the interrupt vector table to ITCM and Stacks into DTCM   for further speed increment for another post which I need to try.

https://community.infineon.com/t5/TRAVEO-T2G/using-DTCM-memory-in-ARM-M7-CYT4BFX-micro-controller/m-... 

Thank you.

Regards,

Bhaskar

[brodynoenow]

Was experiencing the same thing like that and it just automatically corrected itself.