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TRAVEO™ T2G

ICH
Level 2
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Level 2

Hello,

MCU: CYT2B7

according to the Traveo II TRM (revision H)paragraph:

31.4.1 Preconditioning - this is a safe diagnostic feature, which verify the state of the "external" wiring short to GND,VCC and open load.

31.4.3 SARMUX diagnostics - this feature allow verification the connection from SARMUX input pin (I understand this like input physical  pin ) to the sampling capacitor.

According to the AN219755 paragraph 8 Diagnosis function, which explain ADC diagnostic "Overlap diagnostics mode'' is not enabled.

The question:

I would like to do self diagnostic of the ADC, which include the input multiplexer and ADC core.

Is the algorithm explained in the app note AN219755 is suitable for this purpose or other algorithm including SARMUX diagnostics, should be used?

Best regards,

ICH

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Ashish
Moderator
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Moderator

Hi,

Sorry for delay. For the original question-for the testing based on preconditioning, it is assumed that the core is functional, and VrefH , VrefL are correct (there is no option to change the reference voltage  VREFH and VREFL internally to some other pin for testing purpose, so testing it itself won't be possible). Other things can be tested as described earlier.

For your MCAL queries, we suggest to contact local sales representative (as we can't discuss on community). But in general, as I already suggested VrefL/H can't be tested using ADC as the pin is fixed [refer datasheet for the pin]. Although you can provide VrefL/H to ADC channel input, and ideally VRefH should correspond to max digital output typically 0xFFFu and VrefL should correspond to min digital output typically 0x000u [refer the calibration procedure in the Appnote you mentioned, and also register PASSx_SARy_CHz_SAMPLE_CTL [5:0] PIN_ADDR] .

 

Best Reagrds,

Ashish

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Ashish
Moderator
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Moderator

Hi ,

You can achieve the self-test/diagnostic through the preconditioning method which you already mentioned. I attached a screenshot which summarizes the process. By diagnostic here, I mean testing for short to gnd/vdd and open fault. This method will test your input signal from any channel, but you can also provide internal input to the channel, and it should work (you may use diagnostic reference block to provide internal input to sarmux, refer section 31.10, 31.11 in TRM).  

Ashish_0-1636957910680.png

 

Best Regards,

Ashish

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ICH
Level 2
10 replies posted 10 sign-ins 5 replies posted
Level 2

Hi Ashish,

Thank you for you response!

For self test I mean , that the SARMUX  (internal circuit)work properly have to be tested on the desired channel and the ADC core work properly.

The preconditioning feature will test the external circuit (pin input for short and open circuit), using this method the sample capacitor will be pre-charge or discharge, this mean that the internal circuit of the channel ( input pin -> SARMUX -> sample capacitor ) work in this test and it is tested?

After that,  the ADC core is used to measure the sample capacitor state. This mean, that in this stage the ADC core is also tested (because it is used ) ?

For ADC core testing may be it is good ,additional measuring the reference voltages to be implemented for ADC core testing?

Best regards,

ICH

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ICH
Level 2
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Level 2

Hi,

one additional question.

Is it possible to use MCAL for dynamically switching the SARMUX.

For example one logical channel to different input pins (VRFH and BREFL)

Best regards,

ICH

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Ashish
Moderator
Moderator 50 solutions authored 100 replies posted 100 sign-ins
Moderator

Hi,

Sorry for delay. For the original question-for the testing based on preconditioning, it is assumed that the core is functional, and VrefH , VrefL are correct (there is no option to change the reference voltage  VREFH and VREFL internally to some other pin for testing purpose, so testing it itself won't be possible). Other things can be tested as described earlier.

For your MCAL queries, we suggest to contact local sales representative (as we can't discuss on community). But in general, as I already suggested VrefL/H can't be tested using ADC as the pin is fixed [refer datasheet for the pin]. Although you can provide VrefL/H to ADC channel input, and ideally VRefH should correspond to max digital output typically 0xFFFu and VrefL should correspond to min digital output typically 0x000u [refer the calibration procedure in the Appnote you mentioned, and also register PASSx_SARy_CHz_SAMPLE_CTL [5:0] PIN_ADDR] .

 

Best Reagrds,

Ashish

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ICH
Level 2
10 replies posted 10 sign-ins 5 replies posted
Level 2

Hi, thank you very much for the response!

I measure external reference voltages VREFL and VREFH with the ADC (pin_addr 62 and 63).

There is a diagnosis app, which explain this procedure. May be I do not understand something.

If I measure external VREFH, how it is possible to expect value under 4095?

The measured signal and the reference are the some signal?

Application note AN219555 paragraph 8.

Best regards,

 

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ICH
Level 2
10 replies posted 10 sign-ins 5 replies posted
Level 2

Hi,

one additional question.

If the global for ADC unit settings "DIAG_EN" and "EPASS_MMIO.PASS_CTL.REFBUF_EN" are set for diagnostic purposes, are those settings affect on all ADC groups (channels). For example I want to use only two channels per unit for diagnostic purposes.

Best rgeards,

 

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