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ICH
Level 2
Level 2
10 replies posted 10 sign-ins 5 replies posted

Hi,

MCU CYT2B75

If the global for ADC unit settings "DIAG_EN" and "EPASS_MMIO.PASS_CTL.REFBUF_EN" are set for diagnostic purposes, are those settings affect on all ADC groups (channels). For example I want to use only two channels per unit for diagnostic purposes.

Best rgeards,

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1 Solution
JJack
Level 5
Level 5
50 sign-ins 10 likes received 25 replies posted

Hi,

for my understanding it is like this:

  • There is one register PASS0_PASS_CTL with field REFBUF_MODE for the Programmable Analog SubSystem 0 (PASS0). And on this chip there is only one PASS, i.e. PASS0. The setting of this register affects all SAR instances in PASS0. Setting REFBUF_MODE to 1 or 3 is the prerequisite for SARMUX diagnostics with SAR.DIAG_CTL.DIAG_EN.
  • Every SAR instance has their own register PASS_SARx_DIAG_CTL with fields DIAG_EN and DIAG_SEL. Settings in PASS_SAR0_DIAG_CTL are potentially effective to all channels of SAR0. Enabling DIAG_EN for SAR0 is the prerequisite to inject the diagnostic reference signal to a channel of the SARMUX of SAR0.
  • When the above mentioned prerequisites have been enabled, then the PASS_SAR0_CHx_SAMPLE_CTL.OVERLAP_DIAG can be set to 1, 2 or 3 to test the SARMUX for channelx. I guess you want to use OVERLAP_DIAG = 3 to feed the diagnostic reference signal through to the SAR.

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13 Replies
JJack
Level 5
Level 5
50 sign-ins 10 likes received 25 replies posted

Hi,

for my understanding it is like this:

  • There is one register PASS0_PASS_CTL with field REFBUF_MODE for the Programmable Analog SubSystem 0 (PASS0). And on this chip there is only one PASS, i.e. PASS0. The setting of this register affects all SAR instances in PASS0. Setting REFBUF_MODE to 1 or 3 is the prerequisite for SARMUX diagnostics with SAR.DIAG_CTL.DIAG_EN.
  • Every SAR instance has their own register PASS_SARx_DIAG_CTL with fields DIAG_EN and DIAG_SEL. Settings in PASS_SAR0_DIAG_CTL are potentially effective to all channels of SAR0. Enabling DIAG_EN for SAR0 is the prerequisite to inject the diagnostic reference signal to a channel of the SARMUX of SAR0.
  • When the above mentioned prerequisites have been enabled, then the PASS_SAR0_CHx_SAMPLE_CTL.OVERLAP_DIAG can be set to 1, 2 or 3 to test the SARMUX for channelx. I guess you want to use OVERLAP_DIAG = 3 to feed the diagnostic reference signal through to the SAR.
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ICH
Level 2
Level 2
10 replies posted 10 sign-ins 5 replies posted

Hi,

thank you very much for your reply.

I have to implement ADC functional safety  feature, which test the ADC core and input multiplexer, that they work correctly. For this reason I start to implement the algorithm explained in the AN219755 paragraph 8 (Diagnosis function). In this test VREFL and VREFH are measured, PASS_PASS_CTL ->REFBUFF_MODE = 1 and DIAG is enabled.

I have some questions:

1. Whit this configuration  the input pins VREFH and VREFL are measured (pinaddr 62 and 63 for SAR0)?

In this case, which is the reference voltage for this measurement.

What is the measurement path?

2. Is this test configuration, test and the input multiplexer functionality?

3. If those settings are applied for tests, is it necessary to change the configuration, when the regular ADC measurement is executed?

Best regards,

 

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JJack
Level 5
Level 5
50 sign-ins 10 likes received 25 replies posted

Ralf_0-1640188401302.png

In header file cy_adc.h CY_ADC_PIN_ADDRESS_VREF_H is set to 63u.

63u means

Ralf_1-1640188570553.png

So this is ok for a plausibility test of the SAR but not for the SARMUX because it is bypassed. The measurement path has nothing to do with the ANin GPIO pins. According to the documentation it is the direct path from pin VREFH to the input of the SAR.

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ICH
Level 2
Level 2
10 replies posted 10 sign-ins 5 replies posted

Hello Ralf,

thank you for your response!

Yes, I implement this measurement (internal) like a test for SAR0 (PIN_ADDR 62 and 63) for SAR1(PIN_ADDR 126 and 127), for SAR1(PIN_ADDR  190 and 191). But for now in my configuration I do not set PASS_PASS_CTL ->REFBUFF_MODE = 1 (Reference buffered Vbg
from SRSS) enable DIAG.

ICH_0-1640244633030.png

1. What is the purpose of enable this two setting, when pre-condition and overlap diagnostic are disabled in this application?

2. What do you prefer to be implemented for functional safety test of the SAR(0,1,2) and SARMUXs? Overlap diagnostic + measurement of the VREFH and VREFL?

3. In my case I must use custom configuration tool and MCAL. The MCAL do not support dynamically change of the register settings. This mean, that the ADC unit configuration is static. 

Thank you in advise!

Best regards,

   

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JJack
Level 5
Level 5
50 sign-ins 10 likes received 25 replies posted

Hello ICH,

1) Hard to say, according to Infineon the Reference Buffer supports four functions
–Power Supply Monitoring
–Buffering the 0.9-V bandgap signal from the System Resource Sub System (SRSS)
–Connects to SAR and diagnostic reference generator multiplexer inputs
–Scaling 1 μA (4x 250 nA currents in parallel) from the SRSS to 10 μA and replicating this current (both source and sink) for diagnostic reference generators. Use case: Broken wire detection
–Providing a temperature-dependent voltage for one-die temperature sensing

2) In my opinion yes, for SARMUX test the overlap diagnostics with OVERLAP_DIAG = 3 (MUX_DIAG) and additionally converting VREFH and VREFL bypassing the SARMUX.

3) Sorry, but I do not feel competent enough for answers on MCAL

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ICH
Level 2
Level 2
10 replies posted 10 sign-ins 5 replies posted

Hi Ralf, thanks!

1. yes in the application Buffering the 0.9-V bandgap signal from the System Resource Sub System (SRSS) is used and DIAG_EN bit is set in PASS_SAR_DIAG_CTL is set.

Is this setting take affect when VREFH and VREL are measured?

When measure VREFH and VREFL (they are measured internally outside of the SAR MUX), but this signals are actually the external signals VREH and VREFL, which are applied on physical pins 44 and 41 for CYT2B75. Am I right? In this case what is the ADC reference to measure this two signals? The exact this signals or I am wrong? If in this case the ADC use external reference voltage applied to the physical pins for ADC reference  and measure this signals, this mean that for VREFH every measurement will be 0xFFF, even the VREFH is 1V, 2V .....5V. 

Best regards,

ICH

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JJack
Level 5
Level 5
50 sign-ins 10 likes received 25 replies posted

Hi ICH,

Is this setting take affect when VREFH and VREL are measured? -> No, doesn't matter.

When measure VREFH and VREFL (they are measured internally outside of the SAR MUX), but this signals are actually the external signals VREH and VREFL, which are applied on physical pins 44 and 41 for CYT2B75. Am I right? -> Yes, I corrected this in my earlier answer. In this case what is the ADC reference to measure this two signals? The exact this signals or I am wrong? -> You are right. If in this case the ADC use external reference voltage applied to the physical pins for ADC reference and measure this signals, this mean that for VREFH every measurement will be 0xFFF, even the VREFH is 1V, 2V .....5V. -> Yes indeed. The app note takes noise and errors into account, so that the expected conversion results have to be greater or equal than a certain limit (0xFEE).

Ralf_0-1640255149343.png

 

 

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ICH
Level 2
Level 2
10 replies posted 10 sign-ins 5 replies posted

Hi Ralf, thank you!

one last question.

According to the SARMUX diagnostic - overlap diagnostics with OVERLAP_DIAG = 3, it verify the path from the input pin to the sample capacitor.  This mean, that this setting (diagnostic) should be done on channel , which have PIN_ADDR, which is part of SARMUX inputs. I can not use the channel, which are configured for VREFH and VREFL measurement for SARMUX diagnostic?                          

Best regards,

ICH

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JJack
Level 5
Level 5
50 sign-ins 10 likes received 25 replies posted

Hi ICH,

According to the SARMUX diagnostic - overlap diagnostics with OVERLAP_DIAG = 3, it verify the path from the input pin to the sample capacitor. This mean, that this setting (diagnostic) should be done on channel , which have PIN_ADDR, which is part of SARMUX inputs.

-> Yes. Checking the header file cyt2b75cae.h I find registers PASS0_SAR0_CH0  to PASS0_SAR0_CH23 available and PASS0_SAR1_CH0  to PASS0_SAR1_CH31 and PASS0_SAR2_CH0  to PASS0_SAR2_CH7. Into every one of these channels you can inject the diagnostic reference individually.

I can not use the channel, which are configured for VREFH and VREFL measurement for SARMUX diagnostic? -> Yes, that is my understanding: you cannot, because these two signals are actually not routed through a channel of the SARMUX.

Ralf_1-1640265436044.png

However, you can make the test anyway by selecting VREFH (or VREFL) as injected diagnostic signal to the input of a SARMUX channel.

Ralf_0-1640264326605.png

 

 

I can not use the channel, which are configured for VREFH and VREFL measurement for SARMUX diagnostic?

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ICH
Level 2
Level 2
10 replies posted 10 sign-ins 5 replies posted

Hi Ralf Thanks!

Happy new year!

I have few questions.

1. What is the value of a AnalogMacro used in Cy_Adc_Diag_Enable(AnalogMacro) - AN219755 Rev G.

2. Reference buffer mode and Diagnosys functions are set only according to using temperature sensor or they have relation to the ADC diagnostic? This continue to not be clear for me.  

Best regards,

 

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JJack
Level 5
Level 5
50 sign-ins 10 likes received 25 replies posted

Hi ICH,

happy new year to you, too!

1. Cy_Adc_Diag_Enable(AnalogMacro) is just a wrapper to set the bit DIAG_EN in the register PASS_SAR_DIAG_CTL. Excerpt from cy_adc.c:

void Cy_Adc_Diag_Enable(volatile stc_PASS_SAR_t * base)
{
  base->unDIAG_CTL.stcField.u1DIAG_EN = 1ul;
}

When calling the function parameter "AnalogMacro" would be replaced by one of the bold printed values below (see header file of the controller, e.g. cyt2b75cae.h), e.g. Cy_Adc_Diag_Enable(PASS0_SAR0);

#define PASS0_SAR0 ((volatile stc_PASS_SAR_t*) &PASS0->SAR[0]) /* 0x40900000 */
#define PASS0_SAR1 ((volatile stc_PASS_SAR_t*) &PASS0->SAR[1]) /* 0x40901000 */
#define PASS0_SAR2 ((volatile stc_PASS_SAR_t*) &PASS0->SAR[2]) /* 0x40902000 */

2. Enabling the REFBUF is a prerequisite for the diagnostic reference of the ADC (and for on-die temperature measurement):

Ralf_0-1641399925271.png

Regards

Ralf

 

2.

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ICH
Level 2
Level 2
10 replies posted 10 sign-ins 5 replies posted

Hi Ralf ,thanks!

I did test with enabled:

Bit DIAG_EN  = 1 on PASS_SAR_DIAG_CTL (SAR0 address 0x40900004)

and

Bit REFBUF_MODE = 1 on PASS_PASS_CTL (address 0x409f0000) 

I can not find a difference between this configuration and without this settings, when measure VREFL and VREFH like analog inputs. 

This two settings are used in AN219755 RevG. In the some document but Rev.B this settings are not used.

May be they have not effect to this measurement?

Best regards,

ICH 

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AS_36
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

Hi @ICH 

We assume that your configured sampling time is sufficient so that both settings are not a problem. 

In case of not using a Reference buffer, VREFL/H actually bypasses the SARMUX. In case of using a Reference buffer, VREL/H is connected to SARMUX though Reference buffer.

If you can get the expected value in user system environment, it will be OK. But if you will check other reference such as Vgap or Temp sensor, we recommend using a Reference buffer.

Regards.

 

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