I2S configuration for CYBT-343026 WICED 6.6

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NaRe_4959971
Level 1
Level 1
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Please let me know regarding the maximum clock and maximum bit of I2S for CYBT-343026 WICED 6.6.
The CYW20706 data sheet states on page 39 that the maximum clock is 3.072MHz for slaves.
Considering this in stereo data, 96kHz x 32bit = 3.072MHz (that is, 96kHz Sampling 16bit LR data),
Is it correct to understand that 48kHz x 48bit = 2.304MHz (that is, 48kHz Sampling 24bit LR data) can also be received?
In that case, how should I set it in WICED 6.6?

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HiNa_2357246
Level 5
Level 5
Distributor - Macnica (Japan)
5 likes given 50 replies posted First like given

You can refer to the link below for I2S configuration on WICED.
https://community.cypress.com/message/214963

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2 Replies
HiNa_2357246
Level 5
Level 5
Distributor - Macnica (Japan)
5 likes given 50 replies posted First like given

You can refer to the link below for I2S configuration on WICED.
https://community.cypress.com/message/214963