20707/20706 GCI pin mapping Coexistence doesn't work.

[JoSt_3481606]

I have had an ongoing problem with 20707/20706 bt modules and enabling the coexistence interface.  I am currently using a CYBT353-20707-02 module.  I can't get the GCI interface to work.  It seems that 20719 parts have a different api that has the calls for mapping the pins to the gci.  The 20707/20706 do not have those apis and only have one bt_coex_enable().  This doesn't seem to work.

It seems missing from the gpio config for these devices.

I have been trying to resolve this for months with no feedback other than look at the app notes.  All the app notes and examples were written using the 20719 or other devices that have the alternate API.

Does this feature work at all?  we chose this part for out design based on the assurance that coexistence is a working feature yet we have not seen it in operation.

Thanks

[AnjanaM_61]

Hello,

The feature should work. 

You just need to call  wiced_bt_coex_enable(); API (in BTM_ENABLED_EVT )

The pins are GPIO_5 and GPIO_6 as mentioned in the datasheet.

Could you please confirm if you are using any custom board for CYBT-35320707-02 module or using CYBT35320707 EVAL board?

If you are using a custom board, can you please confirm if nothing is connected to coex pins.

If EVAL board, I think the GCI pin GPIO_5 is connected to PUART_Rx . Can you please make sure PUART_RX switch is off and try again?

Also which application is running on your wifi chip and CYBT-35320707-02 chip? How you are testing.

I had tested 43907 with 20706 some time back. That time I tested with scan app in 43907 and ble project in 20706. There won't be always signal on the SECI_out of 20706 . I noticed there was some traffic when a scan is starting in 43907 while 20706 tries for a connection etc.

Could you please try out some BT activities during a continuous scan or when scan stops on wifi chip ?

Thanks,

Anjana

[JoSt_3481606]

I do have a custom board but I would just like to see this work with my 2 dev boards CYBT35320707-EVAL and CYW943907AEVAL1F (1GC)

I am running snip.scan on the CYW943907

I am using the default platform files with just one change.

I have flipped the low bit in board flags for the nvram config on the 1GC to enable the GCI and I see data on J6.39 which I have connected to GPIO6 of the CYBT35320707

I am running the beacon snip on the cybt35320707 board with the only code change of adding bt_coex_enable()

GPIO5 of the 20707 board is floating high (3.3) as it should  but when I connected it to J6.38, there is contention and it is pinned at 1.7 volts.   If I disconnect the line, j6.38 is being pulled low on the 1gc

Now it appears that the 1GC board isn't properly setting j6.38 RF_SW_CTRL_8_UART2_RXD as an input.

What would cause that?

[AnjanaM_61 · Accepted solution]

Hello,

As per the internal interactions seems like Coex pins are not brought out for CYBT_353027 module.

I would suggest you to use CYBT_343026 module (https://www.cypress.com/documentation/datasheets/cybt-343026-01-ez-bt-wiced-module ) which uses the same base die (CYW20706) if you are in early stages of product evaluation.

It has Coex pins - GPIO_ 6 & GPIO_7

Sorry for the inconvenience caused.

Thanks & Regards,

Anjana