Specialty Memory Forum Discussions
The customer is considering reducing the power consumption of equipment that is in standby mode for a long period of time.
The power supply to Sync SRAM cannot be stopped because it is shared with other devices.
Therefore, I'm thinking of stopping the clock signal from FPGA to SRAM to reduce power consumption.
1) What is the current consumption of SRAM in Standby: Clock stopped?
2) This SRAM has DOFF# (PLL turn off).
Is it possible to reduce power consumption by setting this pin to High as well?
What is the current consumption with Clock stopped and PLL turned off?
Naoaki MorimotoShow Less
Hello,I run into a problem when using the dual-port SRAM CY7C0852V-133AC.
I want to write some datas to RAM arrays from the left port in write cycle and then read the datas from the right port in read cycle.I set the key signals(like OE、CE0、CE1、RW、CNT_MSK、CNTEN、ADS、CNTRST) accroding to the datasheet(attachment files for more details).
The result is unexpected.When writing 16 datas into array,the right port can read 16 datas accurately.But writing 41 datas into array,the right port can only read 26 datas instead of 41 datas.What's more,if writing 51 datas into array,the right port can only read 16 datas.Is the coincidence?
Please help me! Thank you very much!
There is a user configurable IO standard feature available in CYD36S36V18-200BGXC device. Based on the PORTSTD0, 1 pins the four different IO standards can be selected.
So is it OK to change the IO standard on the Fly and if it is permitteed what are the side effects of it?
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