I saw another discussion on this that had the same exact problem I have, but I was unable to respond. I also didn't see a solution. I am using the Chip CY7C4122KV13. When Writing to the ibis model it is really noisy as if There is no termination. Reading from the model is ok. I am using Hyperlynx. The traces are 50 ohms. I have tried other similar memory models like DDR 3 and it simulates fine. When sending data from my FPGA controller model to the QDRIV memory model it is really noisy.
Is there another model for reading and writing. Is there an error in the Ibis model, or am I missing something?Show Less
i see that Xilinx supports only QDRII+
Do you provide a controller for QDRII and Xilinx ultrascale FPGA?Show Less
I'm using CY7C4122KV13-106FCXC in our design. We need simulation to verify the layout. We downloaded IBIS model from your website. However, we can't pass data write simulation. Your lib for DQ (POD1p2) has only 3 options: QDRIV4122_1PXX_POD1p2DATAIO_60,QDRIV4122_1PXX_POD1p2DATAIO_50 and QDRIV4122_1PXX_POD1p2DATAIO_40. They are good for data read simulation. However, our sim would fail for write. I think when doing writing, ODT should be disabled and proper termination should be connected. So you should have DATAIO models for input simulation. Can you provide me for that? More IBIS models for QDR4?Show Less
We received some CY25422FSXI devices that according to the datasheet are field programmable BUT the devices we received are saying they have already been programmed. We received these devices from Cypress through our customer.
The datasheet(Page 12): http://www.cypress.com/file/137771/download
On page 12 of the datasheet there is a footnote 6 for the field programmable devices which states "The devices mentioned in this datasheet are available as factory-programmable parts and not as field-programmable parts, since the associated programming software is currently not available. Visit www.cypress.com to create a Technical Support case, so Cypress can provide a programming file (.jed file) that matches your requirements."
Is this saying that if we get a CY25422FSXI and CY25422FSXIT device that it is factory programmed and NOT field programmable device? The note is confusing but it might explain why I am getting the device is already programmed message. Please clarify.
The devices I have show this for the marking on the device itself:
Thanks in advance for your assistance.Show Less
If I want to set I/O standard to 2.5V LVCMOS,
I have to use below setting (Table 1. Port Standard Selection)
- PORTSTD1 set VSS
- PORTSTD0 set VTTL
What voltage does it set VTTL?
and How to estimate these current consumption value of VDDIOL/R、VDDCORE、VTTL?Show Less
I am using CYF0018V33L high density FIFO.Input & output width is configured to 32 bits.Requirment is writing to FIFO and reading from fifo at 27MHz rate.Writing to the fifo is continuous and reading is done when 32k words are written.FPGA is used to write to and read from FIFO.Reading is done by generating RE signal when 32k words are written and fpga checks for DVAL signal to be low and value in the output data bus is latched to FPGA.But while analysing data its observerd that in every 32k-4 sample to 32k sample, same sample is repeated (4 cycles).4 words are missing in every set of 32k words.Pls suggest a way to get rid of this connundrum.Show Less
Hello,I run into a problem when using the dual-port SRAM CY7C0852V-133AC.
I want to write some datas to RAM arrays from the left port in write cycle and then read the datas from the right port in read cycle.I set the key signals(like OE、CE0、CE1、RW、CNT_MSK、CNTEN、ADS、CNTRST) accroding to the datasheet(attachment files for more details).
The result is unexpected.When writing 16 datas into array,the right port can read 16 datas accurately.But writing 41 datas into array,the right port can only read 26 datas instead of 41 datas.What's more,if writing 51 datas into array,the right port can only read 16 datas.Is the coincidence?
Please help me! Thank you very much!