I am working on a design which uses a CPLD to control two CYF0018V FIFOs ,what would be ideal would be a behavioural HDL model of the FIFO but in the absence of these I am looking for a timing diagram showing burst rea/write cycles on these devices.The datasheet mentions the fact that they support burst read/writes but I cannot find any further information.

Thanks

Hi,

I am intefacing MPC8641D to CY7C0833AV DPRAM memory using GPCM mode in PowerPC.

I was able to perform Read/Write transactions to the DPRAM.

Now I need to do burst read from DPRAM using UPM mode in PowerPC.

Does the DPRAM (Part No:CY7C0833AV/Density 9-Mbit) supports the burst read/write operation?

Regards

SID

Can anyone tell me what the internal (physical) configuration of the C7C09389 is?

The external interface is 64K x 18 but I imagine that the internal memory array is probably something more 'square'.

We have had a very rare failure in one of our systems that is hard to recreate, and I am trying to determine if we might be occastionally violating some internal boundary condition.  The error has a pattern to it, and this may give me a clue as to the cause.

Thanks!

Cypress is now offering new High-Density (HD) First-In, First-Out (FIFO) memories up to 72Mbit. The HD FIFOs are particularly well-suited for video and imaging applications which require high density and high frequency for effective buffering.

Read more here!