Specialty Memory Forum Discussions

Hello,

About CYD18S18V18-167BBAXI

http://japan.cypress.com/part/cyd18s18v18-167bbaxi

If I want to set I/O standard to 2.5V LVCMOS,

I have to use below setting (Table 1. Port Standard Selection)

- PORTSTD1 set VSS

- PORTSTD0 set VTTL

What voltage does it set VTTL?

and How to estimate these current consumption value of VDDIOL/R、VDDCORE、VTTL?

Dear Sir/Madam

                           I am using CYF0018V33L high density FIFO.Input & output width is configured to 32 bits.Requirment is writing to FIFO and reading from fifo at 27MHz rate.Writing to the fifo is continuous and reading is done when 32k words are written.FPGA is used to write to and read from FIFO.Reading is done by generating RE signal when 32k words are written and fpga checks for DVAL signal to be low and value in the output data bus is latched to FPGA.But while analysing data its observerd that in every 32k-4 sample to 32k sample, same sample is repeated  (4 cycles).4 words are missing in every set of  32k words.Pls suggest a way to get rid of this connundrum.