The CY7C0833V data sheet (Doc# 38-06059 Rev. AA, 8/1/2017) notes in fig 1 that the CE and CE/ pins are not applicable for this part and must be tied off to VSS and VDD, respectively [to always enable them].
No such notes are listed in Table 3. Is this device truly intended to be on a bus by itself as it cannot be deselected?Show Less
If I want to set I/O standard to 2.5V LVCMOS,
I have to use below setting (Table 1. Port Standard Selection)
- PORTSTD1 set VSS
- PORTSTD0 set VTTL
What voltage does it set VTTL?
and How to estimate these current consumption value of VDDIOL/R、VDDCORE、VTTL?Show Less
The customer is now using IDT's 7025PF and we are trying to replace it with Cypress DPRAM.
The customer's board now works on 5.0V, but they are changing it to 3.0V.
Based on the requirements below, is it correct to suggest CY7C025AV-25AXI?
Pin compatible and timing compatible with 7025PF
I am using CYF0018V33L high density FIFO.Input & output width is configured to 32 bits.Requirment is writing to FIFO and reading from fifo at 27MHz rate.Writing to the fifo is continuous and reading is done when 32k words are written.FPGA is used to write to and read from FIFO.Reading is done by generating RE signal when 32k words are written and fpga checks for DVAL signal to be low and value in the output data bus is latched to FPGA.But while analysing data its observerd that in every 32k-4 sample to 32k sample, same sample is repeated (4 cycles).4 words are missing in every set of 32k words.Pls suggest a way to get rid of this connundrum.Show Less
for the CYD36S72V18, what are your recommendations for power supply decoupling and for handling unused pins?
Hello,I run into a problem when using the dual-port SRAM CY7C0852V-133AC.
I want to write some datas to RAM arrays from the left port in write cycle and then read the datas from the right port in read cycle.I set the key signals(like OE、CE0、CE1、RW、CNT_MSK、CNTEN、ADS、CNTRST) accroding to the datasheet(attachment files for more details).
The result is unexpected.When writing 16 datas into array,the right port can read 16 datas accurately.But writing 41 datas into array,the right port can only read 26 datas instead of 41 datas.What's more,if writing 51 datas into array,the right port can only read 16 datas.Is the coincidence?
Please help me! Thank you very much!
There is a user configurable IO standard feature available in CYD36S36V18-200BGXC device. Based on the PORTSTD0, 1 pins the four different IO standards can be selected.
So is it OK to change the IO standard on the Fly and if it is permitteed what are the side effects of it?