Specialty Memory Forum Discussions

 Hello,I run into a problem when using the dual-port SRAM CY7C0852V-133AC.

I want to write some datas to RAM arrays from the left port in write cycle and then read the datas from the right port in read cycle.I set the key signals(like OE、CE0、CE1、RW、CNT_MSK、CNTEN、ADS、CNTRST) accroding to the datasheet(attachment files for more details).
The result is unexpected.When writing 16 datas into array,the right port can read 16 datas accurately.But writing 41 datas into array,the right port can only read 26 datas instead of 41 datas.What's more,if writing 51 datas into array,the right port can only read 16 datas.Is the coincidence?
Please help me! Thank you very much!

Hi,

There is a user configurable IO standard feature available in CYD36S36V18-200BGXC device. Based on the PORTSTD0, 1 pins the four different IO standards can be selected.

So is it OK to change the IO standard on the Fly and if it is permitteed what are the side effects of it?

Regards

Cypress now offers self-paced tutorials on FIFOs. These training modules start out with the fundamentals of FIFO operation and later introduce the special features of these devices and their applications. These tutorials are ideal for beginners as well as for advanced users.

These web-based tutorials can be found in the "Training On-Demand" section of our website:

Asynchronous FIFOs: http://www.cypress.com/?rID=53985

Synchronous FIFOs: www.cypress.com/

Please provide your feedback on these tutorials as it will help us improve the content and quality of the modules.

Thanks!

Hi,

Cypress has recently enhanced the Training Module contents on its website. Please check the following link, for a training module on basics of Synchronous Dual-Port RAM's.

http://www.cypress.com/?rID=12642

Please take these modules at your convenience and let us know your feedback.

Thanks!