Standby current when QDR II+ source clock signal (K, K#) is stopped

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NaMo_1534561
Level 5
Level 5
Distributor - Macnica (Japan)
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Hello,

The customer is considering reducing the power consumption of equipment that is in standby mode for a long period of time.
The power supply to Sync SRAM cannot be stopped because it is shared with other devices.
Therefore, I'm thinking of stopping the clock signal from FPGA to SRAM to reduce power consumption.


1) What is the current consumption of SRAM in Standby: Clock stopped?
2) This SRAM has DOFF# (PLL turn off).
Is it possible to reduce power consumption by setting this pin to High as well?
What is the current consumption with Clock stopped and PLL turned off?


MPN: CY7C2265KV18-550BZXI

Best regards,

Naoaki Morimoto

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