QDRIV ibis Model

[jonduncan]

I saw another discussion on this that had the same exact problem I have, but I was unable to respond. I also didn't see a solution. I am using the Chip CY7C4122KV13.  When Writing to the ibis model it is really noisy as if There is no termination. Reading from the model is ok. I am using Hyperlynx. The traces are 50 ohms. I have tried other similar memory models like DDR 3 and it simulates fine. When sending data from my FPGA controller model to the QDRIV memory model it is really noisy.

Is there another model for reading and writing. Is there an error in the Ibis model, or am I missing something?

[PradiptaB_11]

Hi,

Can you let us know which model you have selected from the IBIS model selector in QDR IV and what model you are using correspondingly on the FPGA side for your simulations. The thread/ post you are referring to also had the same issue. There was a mismatch in model selection and termination used leading to noisy results.

You can read more on termination schemes recommendation on page 23 of the following app note.

https://www.cypress.com/file/46581/download

Thanks and Regards,

Pradipta.

[jonduncan]

Thank you for your response. I am using the CY7C4122KV13 Ibis file. The problem I am having is with the Data pins. The Ibis model for the FPGA was generated in Quartus. For this simulation the FPGA is an output and the QDRIV is an input. The termination I have selected for the FPGA is pod12_rtio_r48cp1_lv which is 48 ohm with calibration with fast slew rate. For the memory side the termination I have selected is Pod1p2DATAIO_50, or Pod 1.2V 50ohms.  The trace is near 50ohms, it is 2.6 inches long.  I am simulating in Hyperlinx. I am running a 1066mhz oscillator on the data signal. The results looks like a triangle wave, not good. I am tried a few other termination options in the ibis model, and the results look simular. I am probably just missing something simple. Thank you.

[PradiptaB_11]

Hi,

Can you add a series resistor for FPGA termination to get it close to 50 and observe the results again. If this does not solve your issue can you pass on the model generated by you for the FPGA. We can try the simulations at our end as well to debug the issue.

Thanks,

Pradipta.

[jonduncan]

I changed the signaling scheme to HSTL with 50 ohm termination. The results are similar, but were a little better. It looks like it isn't terminated, even though I select HSTL with 50 ohm ODT. So I did as you suggested. Putting a resistor in series helps a little but not much. If a put a resistor in parallel to 0.6V, and that seems to work the best. So again it appears the model doesn't have the termination correct or something. The Address pins work fine. And if I set the data pins to outputs that also works fine. It is just if the data pins are input to the QDRIV memory.