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Specialty Memory Forum Discussions

vena_4724751
Level 1
Level 1

Hello All,

     I Am facing issue with CY7C1645KV18 Verilog model simulation with Xilinx MIG generated Test bench. Getting Calibration complete not done error. If anybody facing the issues with Verilog model simulation on this part or any other part?. If yes please suggest the workaround for solving this issue.

Thanks With Regards,

Venkatesh Babu.N

India.

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PradiptaB_11
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

Hi,

We can support you on our created Test bench. You may need to ask Xilinx to provide a clarification to your query as we have not tried MIG generated test bench using Vivado.

Thanks,

Pradipta.

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1 Reply
PradiptaB_11
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

Hi,

We can support you on our created Test bench. You may need to ask Xilinx to provide a clarification to your query as we have not tried MIG generated test bench using Vivado.

Thanks,

Pradipta.

0 Likes