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Specialty Memory Forum Discussions

Anonymous
Not applicable

I am working on a design which uses a CPLD to control two CYF0018V FIFOs ,what would be ideal would be a behavioural HDL model of the FIFO but in the absence of these I am looking for a timing diagram showing burst rea/write cycles on these devices.The datasheet mentions the fact that they support burst read/writes but I cannot find any further information.

   

 

   

Thanks

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1 Solution
AdithiP_46
Employee
Employee
5 replies posted First question asked First solution authored

Hi Jezmo,

   

The burst writes mentioned in the single queue HDFIFO CYF0018V datasheet indicate that the HDFIFO can be written to only in bursts of two.  There is no such restriction on the number of reads(odd or even) performed on the HDFIFO. I request you to clarify if you are looking for any other specific information regarding the burst writes and reads to the device.

   

Thanks & Regards,

   

Adithi

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2 Replies
AdithiP_46
Employee
Employee
5 replies posted First question asked First solution authored

Hi Jezmo,

   

The burst writes mentioned in the single queue HDFIFO CYF0018V datasheet indicate that the HDFIFO can be written to only in bursts of two.  There is no such restriction on the number of reads(odd or even) performed on the HDFIFO. I request you to clarify if you are looking for any other specific information regarding the burst writes and reads to the device.

   

Thanks & Regards,

   

Adithi

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Anonymous
Not applicable

Hi,

   

I take it from the answer to this question that there exists no VHDL model of the FIFO?

   

A model would be very useful as the part appears non-trivial, especially with all the latencies.

   

Thanks.

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