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AURIX™ Development Studio
The AURIX™ Development Studio is a free of charge Integrated Development Environment (IDE) for the TriCore™-based AURIX™ microcontroller family. It is a comprehensive development environment, including Eclipse IDE, C-Compiler, Multi-core Debugger, Infineon low-level driver (iLLD), with no time and code-size limitations that enables editing, compiling, and debugging of application code. Combined with numerous code example projects, the IDE can be used to evaluate the powerful architecture of the AURIX™ microcontroller family. It supports Microsoft Windows 10 as a host operating system (OS).
I have been out of the PSoC loop for a while, and want to get started with it again.
Unfortunately I have run into a problem.
I have a PSoC ICE-4000 with USB-4000 usb adapter, which all worked perfectly under designer 4.2
However I now installed (on a new PC) Designer 5.0, which basically seems to refuse to work with anything else than a ICE-CUBE.
After some searching, I have found and installed the PSoC Progammer utility, which enables me to program a PSoC using the ICE-4000. This also works inside Designer 5.0, but I still am unable to select, configure and use the ICE functionality.
Does anyone know how I can get my ICE-4000 up and running under Designer 5.0 ?
Thanks in advance.
Robin Stevenhagen Show Less
What is the deal? Why has it been nuked? Show Less
issp cy8c29666 mycode.hex -p -n
This does not seem to work.
The green and red lights flash briefly, then go off; the status flashes for a bit (as it does when using the ISSP from its GUI), then (after not long enough time to do the programming), the red light comes on. Programming this part from the GUI works fine.
The program appears to be returning an ERRORLEVEL of zero, supposedly signifying success.
Also, BTW, the documentation says there is a file issp.bat with the distribution - that does not appear to be the case. Show Less
- PSoC doing CSD as its main task
- communication to master via SPIS
- SPIS switched of during CSD
(because sales man from cypress says irq from SPIS may corrupt CSD sample)
- SPIS multiple bytes in each cycle (e.g. 4 bytes)
- SPIS using software SS
- SPIS irq not enabled, polling
- PSoC slave is only sending, not receiving
- clocks from SPI master in cyclic packets (for the multiple bytes)
- PSoC-slave may start listening to SPIS in the middle of a clock packet
and may therefore not be able to send all its multiple bytes out, so using timeouts
for first byte, for other each byte, for all bytes. If timeout occures speeping to
synchronize on next clock packet.
1. documentation says:
"On the falling edge of the Slave Select signal, the data is transferred from the Tx Buffer register to the Shift register."
Finding: SPIS_EnableSS() and SPIS_DisableSS() have no influence on when TX data buffer is transfered to shift register.
2. documentation says:
"Data to be transmitted to the SPI Master is written to the Tx Buffer register. This clears the Tx Buffer Empty status bit."
Finding: On first SPIS_SetupTxData(...) data is automaticaly/imediatetly transfered to shift register and TX_BUFFER_EMPTY flag is therefore set.
On second SPIS_SetupTxData(...) data stays in TX data buffer and TX_BUFFER_EMPTY flag is reset.
3. documentation says:
"SPIS_bReadStatus ... Side Effects: The status bits are cleared after this function is called."
Finding: SPIS_bReadStatus() has no influence on status bit TX_BUFFER_EMPTY.
I have a problem with 1. How can i controll when TX data buffer is transfered to shift register, by my selfe?
What is the difference of TX_BUFFER_EMPTY and SPI_COMPLETE flag?
"Choosing the second option, "TxComplete," delays the interrupt until the last bit is shifted out of the Shift register."
But shift register is automatically loaded from TX data buffer when every bit of it has been shifted out (SPI_COMPLETE will be signaled) and then also SPI_COMPLETE flag would be set, or?
How could i tell the SPIS state machine that it should ignore the data automaticaly transfered from TX data buffer and go directly to the state when shift register is empty?
I think software has too low influence on the state machine.
State machine is not documentet correctly/enough.
A state diagram would be very helpfull.
Michael Show Less
How do I correct this? Thanks. Show Less
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